1
Features
Single-voltage Operation
–5V Read
5V Programming
Fast Read Access Time – 70 ns
Internal Erase/Program Control
Sector Architecture
One 8K Word (16K Bytes) Boot Block with Programming Lockout
Two 4K Word (8K Bytes) Parameter Blocks
One 496K Word (992K Bytes) Main Memory Array Block
Fast Sector Erase Time – 10 seconds
Byte-by-byte or Word-by-word Programming – 10 µs Typical
Hardware Data Protection
Data Polling for End of Program Detection
Low Power Dissipation
50 mA Active Current
100 µA CMOS Standby Current
Typical 10,000 Write Cycles
Description
The AT49F008A(T) and AT49F8192A(T) are 5-volt, 8-megabit Flash memories orga-
nized as 1,048,576 words of 8 bits each or 512K words of 16 bits each. Manufactured
with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times
to 90 ns with power dissipation of just 275 mW. When deselected, the CMOS standby
current is less than 100 µA.
The device contains a user-enabled “boot block” protection feature. Two versions of
the feature are available: the AT49F008A/8192A locates the boot block at lowest
order addresses (“bottom boot”); the AT49F008AT/8192AT locates it at highest order
addresses (“top boot”).
To allow for simple in-system reprogrammability, the AT49F008A(T)/8192A(T) does
not require high-input voltages for programming. Reading data out of the device is
similar to reading from an EPROM; it has standard CE
, OE and WE inputs to avoid
bus contention. Reprogramming the AT49F008A(T)/8192A(T) is performed by first
erasing a block of data and then programming on a byte-by-byte or word-by-word
basis.
8-megabit
(1M x 8/
512K x 16)
Flash Memory
AT49F008A
AT49F008AT
AT49F8192A
AT49F8192AT
Rev. 1199G–FLASH–11/02
Pin Configurations
Pin Name Function
A0 - A18 Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET Reset
RDY/BUSY
Ready/Busy Output
I/O0 - I/O14 Data Inputs/Outputs
I/O15 (A-1)
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
BYTE
Selects Byte or Word Mode
NC No Connect
2
AT49F008A(T)/8192A(T)
1199G–FLASH–11/02
AT49F8192A(T) TSOP Top View
Type 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE
GND
I/O15 / A-1
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
AT49F008A(T) TSOP Top View
Type 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A16
A15
A14
A13
A12
A11
A9
A8
WE
RESET
NC
RDY/BUSY
A18
A7
A6
A5
A4
A3
A2
A1
A17
GND
NC
A-1
A10
I/O7
I/O6
I/O5
I/O4
VCC
VCC
NC
I/O3
I/O2
I/O1
I/O0
OE
GND
CE
A0
AT49F8192A(T) SOIC (SOP) Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
I/O0
I/O8
I/O1
I/O9
I/O2
I/O10
I/O3
I/O11
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
Note: “•” denotes a white dot marked on the package.
The device is erased by executing the Erase command sequence; the device internally con-
trols the erase operation. The memory is divided into four blocks for erase operations. There
are two 4K word parameter block sections: the boot block, and the main memory array block.
The typical number of program and erase cycles is in excess of 10,000 cycles.
The optional 8K word boot block section includes a reprogramming lockout feature to provide
data integrity. This feature is enabled by a command sequence. Once the boot block program-
ming lockout feature is enabled, the data in the boot block cannot be changed when input
levels of 5.5 volts or less are used. The boot sector is designed to contain user secure code.
For the AT49F8192A(T), the BYTE
pin controls whether the device data I/O pins operate in
the byte or word configuration. If the BYTE
pin is set at a logic “1” or left open, the device is in
word configuration, I/O0 - I/O15 are active and controlled by CE
and OE.
If the BYTE
pin is set at logic “0”, the device is in byte configuration, and only data I/O pins
I/O0 - I/O7 are active and controlled by CE
and OE. The data I/O pins I/O8 - I/O14 are tri-
stated and the I/O15 pin is used as an input for the LSB (A-1) address function.
3
AT49F008A(T)/8192A(T)
1199G–FLASH–11/02
AT49F008A(T)
Block Diagram
AT49F8192A(T)
Block Diagram
Device
Operation
READ: The AT49F008A(T)/8192A(T) is accessed like an EPROM. When CE and OE are low
and WE
is high, the data stored at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high-impedance state whenever CE
or OE
is high. This dual line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or
standby mode, depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the Command Definitions table (I/O8 - I/O15 are don’t care inputs for
the command codes). The command sequences are written by applying a low pulse on the
WE
or CE input with CE or WE low (respectively) and OE high. The address is latched on the
falling edge of CE
or WE, whichever occurs last. The data is latched by the first rising edge of
CE
or WE. Standard microprocessor write timings are used. The address locations used in the
command sequences are not affected by entering the command sequences.
VCC
GND
OE
CONTROL
LOGIC
DATA INPUTS/OUTPUTS
I/O0 - I/O7
DATA INPUTS/OUTPUTS
I/O0 - I/O7
WE
CE
RESET
ADDRESS
INPUTS
Y DECODER
INPUT/OUTPUT
BUFFERS
INPUT/OUTPUT
BUFFERS
PROGRAM DATA
LATCHES
PROGRAM DATA
LATCHES
Y-GATING
AT49F008A AT49F008AT
Y-GATING
FFFFF FFFFF
MAIN MEMORY
(992K BYTES)
BOOT BLOCK
16K BYTES
PARAMETER
BLOCK 2
8K BYTES
PARAMETER
BLOCK 1
8K BYTES
PARAMETER
BLOCK 1
8K BYTES
PARAMETER
BLOCK 2
8K BYTES
BOOT BLOCK
16K BYTES
MAIN MEMORY
(992K BYTES)
08000
07FFF
FC000
FBFFF
06000
05FFF
FA000
F9FFF
X DECODER
04000
03FFF
F8000
F7FFF
00000 00000
VCC
GND
OE
CONTROL
LOGIC
DATA INPUTS/OUTPUTS
I/O0 - I/O15
DATA INPUTS/OUTPUTS
I/O0 - I/O15
WE
CE
RESET
ADDRESS
INPUTS
Y DECODER
INPUT/OUTPUT
BUFFERS
INPUT/OUTPUT
BUFFERS
PROGRAM DATA
LATCHES
PROGRAM DATA
LATCHES
Y-GATING
AT49F8192A AT49F8192AT
Y-GATING
7FFFF 7FFFF
MAIN MEMORY
(496K WORDS)
BOOT BLOCK
8K WORDS
PARAMETER
BLOCK 2
4K WORDS
PARAMETER
BLOCK 1
4K WORDS
PARAMETER
BLOCK 1
4K WORDS
PARAMETER
BLOCK 2
4K WORDS
BOOT BLOCK
8K WORDS
MAIN MEMORY
(496K WORDS)
04000
03FFF
7E000
7DFFF
03000
02FFF
7D000
7CFFF
X DECODER
02000
01FFF
7C000
7BFFF
00000 00000

AT49F8192A-90TI

Mfr. #:
Manufacturer:
Description:
IC FLASH 8M PARALLEL 48TSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet