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PCK9447BD,157

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
9397 750 12522 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 01 — 13 October 2005 7 of 17
Philips Semiconductors
PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
[1] Dynamic characteristics apply for parallel output termination of 50 Ω to V
TT
.
[2] Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference
input pulse width, output duty cycle, and maximum frequency specifications. CCLK0, CCLK1; 0.7 V to 1.7 V.
[3] Setup and hold times are referenced to the falling edge of the selected clock signal input.
[4] Pulse skew time is the absolute difference of the propagation delay times: | t
PLH
–t
PHL
|.
Table 9: Dynamic characteristics (2.5 V)
T
amb
=
−
40
°
C to +85
°
C; V
CC
= 2.5 V
±
5%
[1] [2]
Symbol Parameter Conditions Min Typ Max Unit
f
i
input frequency 0 - 350 MHz
f
o
output frequency 0 - 350 MHz
t
W(i)(ref)
reference input pulse width 1.4 - - ns
t
PLH
, t
PHL
propagation delay CCLK0 or CCLK1 to any Q 1.7 - 4.4 ns
t
PLZ
, t
PHZ
output disable time - - 11 ns
t
PZL
, t
PZH
output enable time - - 11 ns
t
su
setup time CCLK0 or CCLK1 to CLK_STOP
[3]
0.0 - - ns
t
h
hold time CCLK0 or CCLK1 to CLK_STOP
[3]
1.0 - - ns
t
sk(o)
output skew time output-to-output - - 150 ps
t
sk(pr)
process skew time part-to-part - - 2.7 ns
t
sk(p)
pulse skew time (output)
[4]
- - 200 ps
δ
o
output duty cycle f
q
< 170 MHz; δ
ref
= 50 % 45 50 55 %
t
r
, t
f
output rise/fall time 0.6 V to 1.8 V 0.1 - 1.0 ns
Fig 3. Output clock stop (CLK_STOP) timing diagram
CCLK0
or
CCLK1
CLK_STOP
Q0 to Q8
002aaa717
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs.
Fig 4. Cycle-to-cycle jitter time
002aab293
t
N
t
N+1
t
jit(cc)
= | t
N
− t
N+1
|
9397 750 12522 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 01 — 13 October 2005 8 of 17
Philips Semiconductors
PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
Fig 5. Propagation delay (t
PD
) test reference Fig 6. Pulse skew time (t
sk(p)
) test reference
The pin-to-pin skew is defined as the worst-case
difference in propagation delay between any similar
delay path within a single device.
The time from the output controlled edge to the
non-controlled edge, divided by the time between
output controlled edges, expressed as a percentage.
Fig 7. Output skew time (t
sk(o)
) Fig 8. Output Duty Cycle (δ
o
)
(1) 2.4 V (V
CC
= 3.3 V)
1.8 V (V
CC
= 2.5 V)
(2) 0.55 V (V
CC
= 3.3 V)
0.6 V (V
CC
= 2.5 V)
Fig 9. Output transition time test reference Fig 10. Setup and hold time (t
su
, t
h
)
002aab288
t
PD
CCLK
Qn
V
CC
V
CC
/2
GND
V
CC
V
CC
/2
GND
002aab290
t
PLH
CCLK
Qn
V
CC
V
CC
/2
GND
V
CC
V
CC
/2
GND
t
PHL
t
sk(p)
= | t
PLH
− t
PHL
|
002aab289
t
sk(o)
V
CC
V
CC
/2
GND
V
CC
V
CC
/2
GND
t
sk(o)
002aab291
t
P
V
CC
V
CC
/2
GND
T
0
δ = (t
P
÷ T
0
× 100 %)
002aab292
t
f
(1)
(2)
t
r
002aab294
t
su
CCLK0
CCLK1
CLK_STOP
V
CC
V
CC
/2
GND
V
CC
V
CC
/2
GND
t
h
9397 750 12522 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 01 — 13 October 2005 9 of 17
Philips Semiconductors
PCK9447
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
9. Application information
9.1 Driving transmission lines
The PCK9447 clock driver was designed to drive high-speed signals in a terminated
transmission line environment. To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance possible. With an output
impedance of 17 Ω (V
CC
= 3.3 V) or 19 Ω (V
CC
= 2.5 V), the outputs can drive either
parallel or series terminated transmission lines.
In most high performance clock networks, point-to-point distribution of signals is the
method of choice. In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel technique terminates the signal at
the end of the line with a 50 Ω resistance to V
CC
/2. This technique draws a fairly high level
of DC current, and thus only a single terminated line can be driven by each output of the
PCK9447 clock driver. For the series terminated case, however, there is no DC current
draw, thus the outputs can drive multiple series terminated lines. Figure 11, illustrates an
output driving a single series terminated line versus two series terminated lines in parallel.
When taken to its extreme, the fan-out of the PCK9447 clock driver is effectively doubled
due to its capability to drive multiple lines.
The waveform plots of Figure 12 show simulation results of an output driving a single line
versus two lines. In both cases the drive capability of the PCK9447 output buffer is more
than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay
measurement in the simulations a delta of only 43 ps exists between the two differently
loaded outputs. This suggests that the dual line driving need not be used exclusively to
maintain the tight output-to-output skew of the PCK9447. The output waveform in
Figure 12 shows a step in the waveform; this step is caused by the impedance mismatch
seen looking into the driver. The parallel combination of the 33 Ω series resistor plus the
output impedance does not match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
Fig 11. Single versus dual transmission lines
Z
o
= 50 Ω
002aaa718
R
S
= 33 Ω
Z
o
= 50 Ω
R
S
= 33 Ω
PCK9447
OUTPUT
BUFFER
OutB1
OutB0
17 Ω
Z
o
= 50 Ω
R
S
= 33 Ω
PCK9447
OUTPUT
BUFFER
OutA
17 Ω
IN
IN
V
L
V
S
Z
O
R
S
R
O
Z
0
++
--------------------------------


=
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

PCK9447BD,157

Mfr. #:
Buy PCK9447BD,157
Manufacturer:
NXP Semiconductors
Description:
IC CLK BUFFER 2:9 350MHZ 32LQFP
Lifecycle:
New from this manufacturer.
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