MC100LVEL34DR2G

MC100LVEL34
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Table 6. 100LVEL DC CHARACTERISTICS, NECL V
CC
= 0 V, V
EE
= −3.8 V to −3.0 V (Note 5)
Symbo
l
Characteristic
−40°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
I
EE
Power Supply Current 23 30 40 23 30 40 23 30 40 mA
I
EE
Power Supply Current 40 50 60 40 50 60 42 52 62 mA
V
OH
Output HIGH Voltage (Note 6) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV
V
OL
Output LOW Voltage (Note 6) −1995 −1700 −1575 −1995 −1700 −1575 −1995 −1700 −1575 mV
V
IH
Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV
V
IL
Input LOW Voltage (Single−Ended) −1995 −1625 −1995 −1625 −1995 −1625 mV
V
BB
Output Voltage Reference −1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 7)
V
EE
+ 1.2 0.0 V
EE
+ 1.2 0.0 V
EE
+ 1.2 0.0 V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current D
D
0.5
−150
0.5
−150
0.5
−150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V
CC
.
6. All loading with 50 W to V
CC
− 2.0 V.
7. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
Table 7. AC CHARACTERISTICS V
CC
= 0 V; V
EE
= −3.0 V to −5.5 V or V
CC
= 3.0 V to 5.5 V; V
EE
= 0 V (Note 8)
Symbo
l
Characteristic
−40°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
f
max
Maximum Toggle Frequency (Figure 4) 1.5 1.5 1.5 GHz
t
PLH
t
PHL
Propagation CLK to Q0, Q1, Q2
Delay to Output MR to Q
550
500
650
600
1000
1000
600
550
700
650
1000
1000
650
600
750
700
1000
1000
ps
t
JITTER
Cycle−to−Cycle Jitter (Figure 4) < 1 < 1 < 1 ps
t
S
Setup Time EN 150 50 150 50 150 50 ps
t
H
Hold Time EN 200 100 200 100 200 100 ps
t
RR
Set/Reset Recovery 300 200 300 200 300 200 ps
V
PP
Input Swing (Note 9) 150 1000 150 1000 150 1000 mV
t
r
t
f
Output Rise/Fall Times Q
(20% − 80%)
120 170 400 140 180 400 160 200 400 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
9. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of [40.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
MC100LVEL34
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There are two distinct functional relationships between the Master Reset and Clock:
CASE 1: If the MR is deasserted (H−L), while the Clock is still high, the
outputs will follow the second ensuing clock rising edge.
CLK
Q0
Q1
Q2
EN
The EN signal will “freeze” the internal divider flip−flops on the first falling edge of CLK after its assertion. The interna
l
divider flip−flops will maintain their state during the freeze. When EN is deasserted (LOW), and after the next falling edg
e
of CLK, then the internal divider flip−flops will “unfreeze” and continue to their next state count with proper phase rela
-
tionships.
Internal Clock
Disabled
Internal Clock
Enabled
MR
CLK
Q0
Q1
Q2
EN
Internal Clock
Disabled
Internal Clock
Enabled
MR
CASE 2: If the MR is deasserted (H−L), after the Clock has transitioned low, the
outputs will follow the third ensuing clock rising edge.
CASE 1 CASE 2
Figure 2. Timing Diagrams
CLOCK
OUTPUT
MR
T
RR
CLOCK
OUTPUT
MR
T
RR
Figure 3. Reset Recovery Time
MC100LVEL34
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6
0
100
200
300
400
500
600
700
800
900
0 500 1000 1500
Figure 4. F
max
/Jitter
FREQUENCY (MHz)
1
2
3
4
5
6
7
8
9
V
OUTpp
(mV)
B4 / 8
B2
JITTER
OUT
ps (RMS)
Figure 5. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q D
Z
o
= 50 W
Z
o
= 50 W
50 W 50 W
V
TT
V
TT
= V
CC
− 2.0 V

MC100LVEL34DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Generators & Support Products HF ECL CLOCK GEN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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