AD260
–6–
REV. 0
t
ff
37%
63%
OUTPUT
INPUT
POSITIVE GOING
INPUT THRESHOLD
NEGATIVE GOING
INPUT THRESHOLD
HYSTERESIS
t
PD
t
PLH
t
PD
t
PHL
+3V
+2V
PROPAGATION DELAY
BUFFER
DELAY LINE
SCHMITT
TRIGGER
12.5ns
t
PD
100V
5pF
OUTPUT
CAPACITANCE
t
rr
= t
ff
= 100V x C
TOTAL OUTPUT CAPACITANCE
>0.5ns – NO LOAD
= 5.5ns INTO 50pF
5pF
INPUT
CAPACITANCE
TOTAL DELAY = (t
PLH
OR t
PHL
) = t
PD
+ (t
rr
OR t
ff
) >13ns (NO LOAD), 18ns (50pF LOAD)
EFFECTIVE CIRCUIT MODEL FOR ONE ISOLATED LOGIC LINE
Figure 2. Typical Timing and Delay Models
(Continued from page 1)
Integral Isolated Power: The AD260 includes an integral,
uncommitted and flexible 1 Watt power transformer for devel-
oping isolated field power sources.
Field and System Enable Functions: Both the isolated and
nonisolated sides of the AD260 have ENABLE pins that three-
state all outputs. Upon reenabling these pins, all outputs are
updated to reflect the current input logic level.
CE Certifiable: Simply by adding the external bypass capacitors
at the supply pins, the AD260 can attain CE certification in
most applications (to the EMC directive) and conformance to
the low voltage (safety) directive is assured by the EN60950
certification.
GENERAL ATTRIBUTES
The AD260 provides five HCMOS/ACMOS compatible isolated
logic lines with ≥ 10 kV/µs common-mode transient immunity.
The case design and pin arrangement provides greater than
18 mm spacing between field and system side conductors, pro-
viding CSA/IS and IEC creepage spacing consistent with 750 V
mains isolation.
The five unidirectional logic lines have six possible combina-
tions of “ins” and “outs,” or transmitter/receiver pairs; hence
there are six AD260 part configurations (see Table I).
Each 20 MHz logic line
has a Schmidt trigger input and a three-
state output (on the other side of the isolation barrier) and 14 ns of
propagation delay. A single enable pin on either side of the
barrier causes all outputs on that side to go three-state and all
inputs (driven pins) to ignore their inputs and retain their last
known state.
Note: All unused logic inputs (1–5) should be tied either high or low,
but not left floating.
Edge “fidelity,” or the difference in propagation time for rising
and falling edges, is typically less than ±1 ns.
Power consumption, unlike opto-isolators, is a function of operat-
ing frequency. Each logic line barrier driver requires about 160 µA
per MHz and each receiver 40 µA per MHz plus, of course, 4 mA
total idle current (each side). The supply current diminishes
slightly with increasing temperature (about –0.03%/°C).
The total capacitance spanning the isolation barrier is less than
10 pF.
The minimum width of a pulse that can be accurately coupled
across the barrier is about 25 ns. Therefore the maximum
square-wave frequency of operation is 20 MHz.
Logic information is sent across the barrier as “set-hi/set-lo”
data that is derived from logic level transitions of the input. At
power-up or after a fault condition, an output might not repre-
sent the state of the respective channel input to the isolator. An
internal circuit operates in the background which interrogates all
inputs about every 5 µs and in the absence of logic transitions,
sends appropriate “set-hi” or “set-lo” data across the barrier.
Recovery time from a fault condition or at power-up is thus
between 5 µs and 10 µs.
DATA
RECEIVER
OUTPUT
BUFFER
GATED
TRANSPARENT
LATCH
SCHMITT
TRIGGER
CONTINUOUS
UPDATE CIRCUIT
3.5kV
ISOLATION
BARRIER
DATA IN
ENABLE
ENABLE
OUT
D
G
DATA
TRANSMITTER
Q
Figure 1. Simplified Block Diagram
