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IS61LV6416-10TLI-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
IS61LV6416
IS61LV6416L
4
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
ISSI
®
CAPACITANCE
(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
IS61LV6416
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-8 ns -10 ns -12 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
ICC VDD Dynamic Operating VDD = Max., Com. — 140 — 120 — 100 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 150 — 130 — 110
typ.
(2)
— 105 — 95—75
I
SB1 TTL Standby Current VDD = Max., Com. — 15 — 15 — 15 mA
(TTL Inputs) VIN = VIH or VIL Ind. — 20 — 20 — 20
CE ≥ VIH , f = 0
I
SB2 CMOS Standby VDD = Max., Com. — 5 — 5 — 5 mA
Current (CMOS Inputs) CE ≥ VDD – 0.2V, Ind. — 10 — 10 — 10
VIN ≥ VDD – 0.2V, or typ.
(2)
— 0.5 — 0.5 — 0.5
VIN ≤ 0.2V, f = 0
Note:
1. At f = f
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at V
DD=3.3V, TA=25
o
C. Not 100% Tested.
IS61LV6416L
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-8 ns -10 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
ICC VDD Dynamic Operating VDD = Max., Com. — 100 — 95mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 110 — 105
typ.
(2)
—75 —70
ISB1 TTL Standby Current VDD = Max., Com. — 15 — 15 mA
(TTL Inputs) VIN = VIH or VIL Ind. — 20 — 20
CE ≥ VIH , f = 0
ISB2 CMOS Standby VDD = Max., Com. — 1 — 1 mA
Current (CMOS Inputs) CE ≥ VDD – 0.2V, Ind. — 1.5 — 1.5
VIN ≥ VDD – 0.2V, or typ.
(2)
— 0.05 — 0.05
VIN ≤ 0.2V, f = 0
Note:
1. At f = f
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at V
DD=3.3V, TA=25
o
C. Not 100% Tested.
IS61LV6416
IS61LV6416L
Integrated Silicon Solution, Inc.
5
Rev. I
11/22/05
1
2
3
4
5
6
7
8
9
10
11
12
ISSI
®
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-8 ns -10 ns -12 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 8 — 10 — 12 — ns
tAA Address Access Time — 8 — 10 — 12 ns
tOHA Output Hold Time 3 — 3 — 3 — ns
tACE CE Access Time — 8 — 10 — 12 ns
tDOE OE Access Time — 5 — 5 — 6 ns
tHZOE
(2)
OE to High-Z Output — 5 — 5 — 6 ns
tLZOE
(2)
OE to Low-Z Output 0 — 0 — 0 — ns
tHZCE
(2
CE to High-Z Output 0 4 0 5 0 6 ns
tLZCE
(2)
CE to Low-Z Output 3 — 3 — 3 — ns
tBA LB, UB Access Time — 6 — 6 — 6 ns
tHZB LB, UB to High-Z Output 0 4 0 5 0 6 ns
tLZB LB, UB to Low-Z Output 0 — 0 — 0 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1a and 1b
AC TEST LOADS
Figure 1a. Figure 1b.
319 Ω
30 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
319 Ω
5 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
IS61LV6416
IS61LV6416L
6
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
ISSI
®
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z
DATA VALID
t
HZB
ADDRESS
OE
CE
LB, UB
D
OUT
t
HZCE
t
BA
t
LZB
READ CYCLE NO. 2
(1,3)
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (CS = OE = VIL, UB or LB = VIL)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = V
IL.
3. Address is valid prior to or coincident with CE LOW transition.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

IS61LV6416-10TLI-TR

Mfr. #:
Buy IS61LV6416-10TLI-TR
Manufacturer:
ISSI
Description:
SRAM 1Mb 64Kx16 10ns Async SRAM 3.3v
Lifecycle:
New from this manufacturer.
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