74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 August 2013 3 of 18
NXP Semiconductors
74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
5. Pinning information
5.1 Pinning
Fig 4. Functional diagram
001aac616
Q0
D
FF1
Q
CP
R
D
CP
DSB
DSA
MR
Q1
D
FF2
Q
CP
R
D
Q2
D
FF3
Q
CP
R
D
Q3
D
FF4
Q
CP
R
D
Q4
D
FF5
Q
CP
R
D
Q5
D
FF6
Q
CP
R
D
Q6
D
FF7
Q
CP
R
D
Q7
D
FF8
Q
CP
R
D
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration SO14 and TSSOP14 Fig 6. Pin configuration DHVQFN14
+&74





DDD
+&4
+&74
*1'

7UDQVSDUHQWWRSYLHZ
4 05
4 4
4 4
4 4
'6% 4
*1'
&3
'6$
9
&&





WHUPLQDO
LQGH[DUHD
74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 August 2013 4 of 18
NXP Semiconductors
74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced input one set-up time prior to the LOW-to-HIGH clock transition
= LOW-to-HIGH clock transition
Table 2. Pin description
Symbol Pin Description
DSA 1 data input
DSB 2 data input
Q0 to Q7 3, 4, 5, 6, 10, 11, 12, 13 output
GND 7 ground (0 V)
CP 8 clock input (LOW-to-HIGH, edge-triggered)
MR
9 master reset input (active LOW)
V
CC
14 positive supply voltage
Table 3. Function table
[1]
Operating
modes
Input Output
MR CP DSA DSB Q0 Q1 to Q7
Reset (clear)LXXXLLtoL
Shift H llLq0to q6
H lhLq0to q6
H hl Lq0to q6
H hhHq0to q6
74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 August 2013 5 of 18
NXP Semiconductors
74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 package: P
tot
derates linearly with 8 mW/K above 70 C.
For TSSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: P
tot
derates linearly with 4.5 mW/K above 60 C.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
CC
+0.5 V
[1]
- 20 mA
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
CC
+0.5V
[1]
- 20 mA
I
O
output current 0.5 V < V
O
< V
CC
+0.5V - 25 mA
I
CC
supply current - 50 mA
I
GND
ground current 50 - mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation
[2]
- 500 mW
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC164-Q100 74HCT164-Q100 Unit
Min Typ Max Min Typ Max
V
CC
supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
V
I
input voltage 0 - V
CC
0- V
CC
V
V
O
output voltage 0 - V
CC
0- V
CC
V
T
amb
ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate V
CC
= 2.0 V - - 625 - - - ns/V
V
CC
= 4.5 V - 1.67 139 - 1.67 139 ns/V
V
CC
= 6.0 V--83---ns/V

74HC164D-Q100J

Mfr. #:
Manufacturer:
Nexperia
Description:
Counter Shift Registers 74HC164D-Q100/SO14/REEL 13" Q1
Lifecycle:
New from this manufacturer.
Delivery:
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