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M27W102
Table 7. Read Mode DC Characteristics
(1)
(T
A
= –40 to 85°C; V
CC
= 2.7V to 3.6V; V
PP
= V
CC
)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Symbol Parameter Test Condition Min Max Unit
I
LI
Input Leakage Current
0V ≤
V
IN
≤ V
CC
±10 µA
I
LO
Output Leakage Current
0V ≤ V
OUT
≤ V
CC
±10 µA
I
CC
Supply Current
E
= V
IL
, G = V
IL
,
I
OUT
= 0mA, f = 5MHz,
V
CC
≤
3.6V
15 mA
I
CC1
Supply Current (Standby) TTL
E
= V
IH
1mA
I
CC2
Supply Current (Standby) CMOS
E
> V
CC
– 0.2V,
V
CC
≤
3.6V
15 µA
I
PP
Program Current
V
PP
= V
CC
10 µA
V
IL
Input Low Voltage –0.6
0.2 V
CC
V
V
IH
(2)
Input High Voltage
0.7 V
CC
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4 V
V
OH
Output High Voltage TTL
I
OH
= –400µA
2.4 V
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E
should be decoded and used as the prima-
ry device selecting function, while G
should be
made a common connection to all devices in the
array and connected to the READ
line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, I
CC
, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E
. The magnitude of
transient current peaks is dependent on the ca-
pacitive and inductive loading of the device at the
output. The associated transient voltage peaks
can be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor be used on every device between V
CC
and V
SS
. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
used between V
CC
and V
SS
for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
