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MC74HC595ADTR2G

P1-P3P4-P6P7-P9P10-P12P13-P13
© Semiconductor Components Industries, LLC, 2016
December, 2016 − Rev. 23
1 Publication Order Number:
MC74HC595A/D
MC74HC595A
8-Bit Serial-Input/Serial or
Parallel-Output Shift
Register with Latched
3-State Outputs
High−Performance Silicon−Gate CMOS
The MC74HC595A consists of an 8−bit shift register and an 8−bit
D−type latch with three−state parallel outputs. The shift register
accepts serial data and provides a serial output. The shift register also
provides parallel data to the 8−bit latch. The shift register and latch
have independent clock inputs. This device also has an asynchronous
reset for the shift register.
The HC595A directly interfaces with the SPI serial data port on
CMOS MPUs and MCUs.
Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC
Standard No. 7 A
• Chip Complexity: 328 FETs or 82 Equivalent Gates
• Improvements over HC595
♦ Improved Propagation Delays
♦ 50% Lower Quiescent Power
♦ Improved Input Noise and Latchup Immunity
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
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MARKING DIAGRAMS
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G, G = Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
SOIC−16
TSSOP−16
1
16
HC595AG
AWLYWW
HC
595A
ALYWG
G
1
16
(Note: Microdot may be in either location)
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
QFN16
MN SUFFIX
CASE 485AW
1
595A
ALYWG
G
QFN16*
*V595A marking used for
NLV74HC595AMN1TWG
MC74HC595A
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2
Figure 1. Pin Assignments
116
215
314
413
512
611
710
89
GND
V
CC
SQ
H
GND
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
LATCH CLOCK
OUTPUT ENABLE
A
Q
A
V
CC
SQ
H
RESET
SHIFT CLOCK
Q
E
Q
D
Q
C
Q
B
GND
Q
H
Q
G
Q
F
Q
B
Q
E
Q
D
Q
C
Q
H
Q
G
Q
F
LATCH CLOCK
OUTPUT ENABLE
A
Q
A
RESET
SHIFT CLOCK
SOIC, TSSOP QFN
LOGIC DIAGRAM
SERIAL
DATA
INPUT
14
11
10
12
13
SHIFT
CLOCK
RESET
LATCH
CLOCK
OUTPUT
ENABLE
SHIFT
REGISTER
LATCH
15
1
2
3
4
5
6
7
9
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
SQ
H
A
V
CC
= PIN 16
GND = PIN 8
PARALLEL
DATA
OUTPUTS
SERIAL
DATA
OUTPUT
MC74HC595A
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3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
V
in
DC Input Voltage (Referenced to GND) –0.5 to V
CC
+0.5 V
V
out
DC Output Voltage (Referenced to GND) –0.5 to V
CC
+0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±35 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±75 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature –65 to +150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
260
_C
V
ESD
ESD Withstand Voltage Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
> 3000
> 400
N/A
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any
of these limits are exceeded, device functionality should not be assumed, damage may occur
and reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage
(Referenced to GND)
0 V
CC
V
T
A
Operating Temperature, All Package Types –55 +125
_C
t
r
, t
f
Input Rise and Fall Time V
CC
= 2.0 V
(Figure 1) V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
1000
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
P1-P3P4-P6P7-P9P10-P12P13-P13

MC74HC595ADTR2G

Mfr. #:
Buy MC74HC595ADTR2G
Manufacturer:
ON Semiconductor
Description:
Counter Shift Registers 8-Bit 3 State Shift
Lifecycle:
New from this manufacturer.
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