IDT74SSTUBF32869A
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 12
IDT74SSTUBF32869A 7093/10
CONFIDENTIAL
Timing Requirements Over Recommended Operating Free-Air Temperature
Range
Switching Characteristics Over Recommended Free Air Operating Range
(unless otherwise noted)
Symbol Parameter
V
DD = 1.8V ± 0.1V
UnitsMin. Max.
fCLOCK Clock Frequency 410 MHz
t
W Pulse Duration, CLK, CLK HIGH or LOW 1 ns
t
ACT
1
1 VREF must be held at a valid input voltage level and data inputs must be held at valid logic levels for a
minimum time of t
ACT(max) after RESET is taken HIGH.
Differential Inputs Active Time 10 ns
t
INACT
2
2 VREF, data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum
time of t
INACT(max) after RESET is taken LOW.
Differential Inputs Inactive Time 15 ns
t
SU
Setup
Time
DCS
before CLK↑ , CLK↓, CSR HIGH; CSR before
CLK↑ , CLK
↓, DCS HIGH
0.6
ns
DCS
before CLK↑ , CLK↓, CSR LOW 0.5
DODT, DOCKE, and data before CLK↑ , CLK
↓ 0.5
PAR_IN before CLK↑ , CLK
↓ 0.5
t
H
Hold
Time
DCS
, DODT, DCKE, and data after CLK↑ , CLK↓ 0.4
ns
PAR_IN after CLK↑ , CLK
↓ 0.4
Symbol Parameter
V
DD = 1.8V ± 0.1V
UnitsMin. Max.
fMAX Max Input Clock Frequency 340 MHz
t
PDM
1
1 Design target as per JEDEC specifications.
Propagation Delay, single-bit switching, CLK↑ / CLK
↓ to Qn 1.1 1.5 ns
t
PD
2
2 Production Test. (See Production Test Circuit in TEST CIRCUIT AND WAVEFORM section.)
Propagation Delay, single-bit switching, CLK↑ / CLK
↓ to Qn 0.4 0.8 ns
t
PDMSS
1
Propagation Delay, simultaneous switching, CLK↑ / CLK↓ to Qn 1.6 ns
t
LH LOW to HIGH Propagation Delay, CLK↑ / CLK↓ to PTYERR 1.2 3 ns
t
HL HIGH to LOW Propagation Delay, CLK↑ / CLK↓ to PTYERR 0.4 3 ns
t
PD Propagation Delay from CLK↑ / CLK↓ to PPO 0.5 1.6 ns
t
PHL HIGH to LOW Propagation Delay, RESET↓ to Qn↓ 3ns
t
PLH LOW to HIGH Propagation Delay, RESET↓ to PTYERR↑ 3ns
