MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
_______________________________________________________________________________________ 7
IN_+
IN_-
OUT_
RECEIVER ENABLED
1/4 MAX9125/MAX9126
*50 REQUIRED FOR PULSE GENERATOR.
**WHEN TESTING MAX9126, ADJUST THE PULSE GENERATOR OUTPUT
TO ACCOUNT FOR INTERNAL TERMINATION RESISTOR.
PULSE**
GENERATOR
50*50*
C
L
IN_-
IN_+
OUT_
50%
V
ID
V
OL
V
OH
20%20%
80% 80%
t
PHLD
t
PLHD
t
THL
t
TLH
O (DIFFERENTIAL)
O (DIFFERENTIAL)
50%
NOTE: V
CM =
(V
IN_
- +
V
IN
_+)
2
IN_+
EN
EN
IN_-
OUT_
DEVICE
UNDER
TEST
1/4 MAX9125/MAX9126
C
L
INCLUDES LOAD AND TEST JIG CAPACITANCE.
S
1
= V
CC
FOR t
PZL
AND t
PLZ
MEASUREMENTS.
S
1
= GND FOR t
PZH
AND t
PHZ
MEASUREMENTS.
GENERATOR
50
C
L
R
L
S
1
V
CC
Figure 2. Transition Time and Propagation Delay Test Circuit
Figure 3. Transition Time and Propagation Delay Timing Diagram
Figure 4. High-Z Delay Test Circuit
MAX9125/MAX9126
Fail-Safe
The fail-safe feature of the MAX9125/MAX9126 sets the
output high when:
Inputs are open.
Inputs are undriven and shorted.
Inputs are undriven and terminated.
A fail-safe circuit is important because under these
conditions, noise at the inputs may switch the receiver
and it may appear to the system that data is being
received. Open or undriven terminated input conditions
can occur when a cable is disconnected or cut, or
when the LVDS driver outputs are high impedance. A
short condition can occur because of a cable failure.
The fail-safe input network (Figure 1) samples the input
common-mode voltage and compares it to V
CC
- 0.3V
(nominal). When the input is driven to levels specified in
the LVDS standards, the input common-mode voltage
is less than V
CC
- 0.3V and the fail-safe circuit is not
activated. If the inputs are open or if the inputs are
undriven and shorted or undriven and parallel terminat-
ed, there is no input current. In this case, a pullup resis-
tor in the fail-safe circuit pulls both inputs above V
CC
-
0.3V, activating the fail-safe circuit and forcing the out-
put high.
Applications Information
Power-Supply Bypassing
Bypass the V
CC
pin with high-frequency surface-mount
ceramic 0.1µF and 0.001µF capacitors in parallel, as
close to the device as possible, with the smaller valued
capacitor closest to V
CC
.
Differential Traces
Input trace characteristics affect the performance of the
MAX9125/MAX9126. Use controlled-impedance PC
board traces to match the cable characteristic imped-
ance. The termination resistor is also matched to this
characteristic impedance.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Each channels differential signals should be routed
close to each other to cancel their external magnetic
field. Maintain a constant distance between the differ-
ential traces to avoid discontinuities in differential
impedance. Avoid 90° turns and vias to further prevent
impedance discontinuities.
Cables and Connectors
Transmission media typically have a controlled differen-
tial impedance of 100. Use cables and connectors
Quad LVDS Line Receivers with
Integrated Termination
8 _______________________________________________________________________________________
1.5V
EN WHEN EN = V
CC
EN WHEN EN = GND
OUTPUT WHEN
V
ID
= -100mV
OUTPUT WHEN
V
ID
= +100mV
1.5V
1.5V
0.5V
0.5V
t
PLZ
t
PHZ
t
PZL
t
PZH
1.5V
3V
0
3V
V
CC
V
OL
V
OH
GND
0
50%
50%
Figure 5. High-Z Delay Waveforms
that have matched differential impedance to minimize
impedance discontinuities.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
pick up noise as common mode, which is rejected by
the LVDS receiver.
Termination
The MAX9126 has an integrated termination resistor
connected across the inputs of each receiver. The
value of the integrated resistor is specified in the DC
characteristics.
The MAX9125 requires an external termination resistor.
The termination resistor should match the differential
impedance of the transmission line. Termination resis-
tance values range between 90 and 132, depend-
ing on the characteristic impedance of the transmission
medium.
When using the MAX9125, minimize the distance
between the input termination resistors and the MAX9125
receiver inputs. Use 1% surface-mount resistors.
Board Layout
Keep the LVDS and any other digital signals separated
from each other to reduce crosstalk.
For LVDS applications, use a four-layer PC board that
provides separate power, ground, LVDS signals, and
output signals. Isolate the input LVDS signals from the
output LVCMOS/LVTTL signals to prevent coupling.
Separate the input LVDS signal plane from the LVC-
MOS/LVTTL output signal plane with the power and
ground planes for best results.
Chip Information
TRANSISTOR COUNT: 940
PROCESS: CMOS
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
_______________________________________________________________________________________ 9

MAX9126EUE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
LVDS Interface IC Quad LVDS Line Driver
Lifecycle:
New from this manufacturer.
Delivery:
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