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74ABT373CMTC

P1-P3P4-P6P7-P9P10-P12P13-P13
74ABT373 Octal Transparent Latch with 3-STATE Outputs
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ABT373 Rev. 1.4 4
DC Electrical Characteristics
Notes:
2. For 8-bit toggling, I
CCD
<
0.8mA/MHz.
3. Guaranteed, but not tested.
Symbol Parameter V
CC
Conditions Min. Typ. Max. Units
V
IH
Input HIGH Voltage Recognized HIGH Signal 2.0 V
V
IL
Input LOW Voltage Recognized LOW Signal 0.8 V
V
CD
Input Clamp Diode Voltage Min. I
IN
=
–18mA –1.2 V
V
OH
Output HIGH Voltage Min. I
OH
=
–3mA 2.5 V
I
OH
=
–32mA 2.0
V
OL
Output LOW Voltage Min. I
OL
=
64mA 0.55 V
I
IH
Input HIGH Current Max. V
IN
=
2.7V
(3)
1µA
V
IN
=
V
CC
1
I
BVI
Input HIGH Current
Breakdown Test
Max. V
IN
=
7.0V 7 µA
I
IL
Input LOW Current Max. V
IN
=
0.5V
(3)
–1 µA
V
IN
=
0.0V –1
V
ID
Input Leakage Test 0.0 I
ID
=
1.9µA, All Other Pins
Grounded
4.75 V
I
OZH
Output Leakage Current 0–5.5V V
OUT
=
2.7V, OE
=
2.0V 10 µA
I
OZL
Output Leakage Current 0–5.5V V
OUT
=
0.5V, OE
=
2.0V –10 µA
I
OS
Output Short-Circuit Current Max. V
OUT
=
0.0V –100 –275 mA
I
CEX
Output HIGH Leakage Current Max. V
OUT
=
V
CC
50 µA
I
ZZ
Bus Drainage Test 0.0 V
OUT
=
5.5V, All Others GND 100 µA
I
CCH
Power Supply Current Max. All Outputs HIGH 50 µA
I
CCL
Power Supply Current Max. All Outputs LOW 30 mA
I
CCZ
Power Supply Current Max. OE
=
V
CC
, All Others at V
CC
or Ground
50 µA
I
CCT
Additional
I
CC
/Input
Outputs Enabled Max. V
I
=
V
CC
– 2.1V 2.5 mA
Outputs 3-STATE Enable Input V
I
=
V
CC
– 2.1V 2.5 mA
Outputs 3-STATE Data Input V
I
=
V
CC
– 2.1V,
All Others at V
CC
or Ground
2.5 mA
I
CCD
Dynamic I
CC
No Load
(3)
Max. Outputs OPEN, LE = V
CC
,
OE
= GND
(2)
,
One-Bit Toggling,
50% Duty Cycle
0.12 mA/
MHz
74ABT373 Octal Transparent Latch with 3-STATE Outputs
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ABT373 Rev. 1.4 5
DC Electrical Characteristics
SOIC package.
Notes:
4. Max number of outputs defined as (n). n – 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not
tested.
5. Max number of outputs defined as (n). n – 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not
tested.
6. Max number of data inputs (n) switching. n – 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold
(V
ILD
), 0V to threshold (V
IHD
). Guaranteed, but not tested.
AC Electrical Characteristics
SOIC and SSOP package.
Symbol Parameter V
CC
Conditions
C
L
= 50pF, R
L
= 500Ω Min. Typ. Max. Units
V
OLP
Quiet Output Maximum Dynamic
V
OL
5.0 T
A
= 25°C
(4)
0.4 0.8 V
V
OLV
Quiet Output Minimum Dynamic
V
OL
5.0 T
A
= 25°C
(4)
–1.2 –0.8 V
V
OHV
Minimum HIGH Level Dynamic
Output Voltage
5.0 T
A
= 25°C
(5)
2.5 3.0 V
V
IHD
Minimum HIGH Level Dynamic
Input Voltage
5.0 T
A
= 25°C
(6)
2.0 1.7 V
V
ILD
Maximum LOW Level Dynamic
Input Voltage
5.0 T
A
= 25°C
(6)
0.9 0.6 V
Symbol Parameter
T
A
= +25°C,
V
CC
= +5.0V,
C
L
= 50pF
T
A
= –55°C to +125°C,
V
CC
= 4.5V to 5.5V,
C
L
= 50pF
T
A
= –40°C to +85°C,
V
CC
= 4.5V to 5.5V,
C
L
= 50pF
UnitsMin. Typ. Max. Min. Max. Min. Max.
t
PLH
Propagation Delay
D
n
to O
n
1.9 2.7 4.5 1.0 6.8 1.9 4.5 ns
t
PHL
1.9 2.8 4.5 1.0 7.0 1.9 4.5
t
PLH
Propagation Delay
LE to O
n
2.0 3.1 5.0 1.0 7.7 2.0 5.0 ns
t
PHL
2.0 3.0 5.0 1.5 7.7 2.0 5.0
t
PZH
Output Enable Time 1.5 3.1 5.3 1.0 6.7 1.5 5.3 ns
t
PZL
1.5 3.1 5.3 1.5 7.2 1.5 5.3
t
PHZ
Output Disable Time 2.0 3.6 5.4 1.7 8.0 2.0 5.4 ns
t
PLZ
2.0 3.4 5.4 1.0 7.0 2.0 5.4
74ABT373 Octal Transparent Latch with 3-STATE Outputs
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ABT373 Rev. 1.4 6
AC Operating Requirements
SOIC and SSOP packages.
Extended AC Electrical Characteristics
SOIC package.
Notes:
7. This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described
switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
8. This specification is guaranteed but not tested. The limits represent propagation delay with 250pF load capacitors
in place of the 50pF load capacitors in the standard AC load. This specification pertains to single output switching
only.
9. This specification is guaranteed but not tested. The limits represent propagation delays for all paths described
switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250pF load capacitors in place of the 50pF load
capacitors in the standard AC load.
10. The 3-STATE delay times are dominated by the RC network (500Ω, 250pF) on the output and has been excluded
from the datasheet.
Symbol Parameter
T
A
= +25°C,
V
CC
= +5.0V,
C
L
= 50pF
T
A
= –55°C to +125°C,
V
CC
= 4.5V to 5.5V,
C
L
= 50pF,
T
A
= –40°C to +85°C,
V
CC
= 4.5V to 5.5V
C
L
= 50pF
UnitsMin. Typ. Max. Min. Max. Min. Max.
f
TOGGLE
Max Toggle Frequency 100 100 MHz
t
S
(H) Setup Time, HIGH or
LOW, D
n
to LE
1.5 2.5 1.5 ns
t
S
(L) 1.5 2.5 1.5
t
H
(H) Hold Time, HIGH or
LOW, D
n
to LE
1.0 2.5 1.0 ns
t
H
(L) 1.0 2.5 1.0
t
W
(H) Pulse Width, LE HIGH 3.0 3.3 3.0 ns
Symbol Parameter
T
A
= –40°C to +85°C,
V
CC
= 4.5V to 5.5V,
C
L
= 50pF,
8 Outputs
Switching
(7)
T
A
= –40°C to +85°C,
V
CC
= 4.5V to 5.5V,
C
L
= 250pF
(8)
T
A
= –40°C to +85°C,
V
CC
= 4.5V to 5.5V,
C
L
= 250pF,
8 Outputs
Switching
(9)
UnitsMin. Max. Min. Max. Min. Max.
t
PLH
Propagation Delay,
D
n
to O
n
1.5 5.2 2.0 6.8 2.0 9.0 ns
t
PHL
1.5 5.2 2.0 6.8 2.0 9.0
t
PLH
Propagation Delay,
LE to O
n
1.5 5.5 2.0 7.5 2.0 9.5 ns
t
PHL
1.5 5.5 2.0 7.5 2.0 9.5
t
PZH
Output Enable Time 1.5 6.2 2.0 8.0 2.0 10.5 ns
t
PZL
1.5 6.2 2.0 8.0 2.0 10.5
t
PHZ
Output Disable Time 1.0 5.5
(10) (10)
ns
t
PZL
1.0 5.5
P1-P3P4-P6P7-P9P10-P12P13-P13

74ABT373CMTC

Mfr. #:
Buy 74ABT373CMTC
Manufacturer:
ON Semiconductor / Fairchild
Description:
Latches Octal Trans Latch
Lifecycle:
New from this manufacturer.
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