Broadcom
- 8 -
ACPL-P454 and ACPL-W454 Data Sheet
Switching Specifications
Over recommended temperature (T
A
= 0°C to 70°C) unless otherwise specified
Parameter Symbol Min.
Typ.
a
a. All typicals at T
A
= 25° C.
Max. Units Test Conditions Fig. Notes
Propagation Delay
Time to Logic Low at
Output
t
PHL
— 0.2 0.3 μs T
A
= 25°C Pulse: f = 20 kHz, Duty Cycle = 10%
I
F
= 16 mA, V
CC
= 5.0V
R
L
= 1.9 k, C
L
= 15 pF, V
THHL
= 1.5V
6, 8, 9
b
b. The 1.9 kload represents 1 TTL unit load of 1.6 mA and the 5.6 kpull-up resistor.
—0.2 0.5 —
0.2 0.5 0.7 T
A
= 25°C Pulse: f = 10 kHz, Duty Cycle = 50%
I
F
= 12 mA,
VCC
= 15.0V
R
L
= 20 kC
L
= 100 pF, V
THHL
= 1.5V
6, 10–14
c
c. The RL = 20 kC
L
= 100 pF load represents an IPM (Intelligent Power Mode) load.
0.1 0.5 1.0 —
Propagation Delay
Time to Logic High at
Output
t
PLH
— 0.3 0.5 μs T
A
= 25°C Pulse: f = 20 kHz, Duty Cycle = 10%
I
F
= 16 mA, V
CC
= 5.0V
R
L
= 1.9 kC
L
= 15 pF, V
THHL
= 1.5V
6, 8, 9
b
—0.3 0.7 —
0.3 0.8 1.1 T
A
= 25°C Pulse: f = 10 kHz, Duty Cycle = 50%
I
F
= 12 mA, V
CC
= 15.0V
R
L
= 20 kC
L
= 100 pF, V
THHL
= 2.0V
6, 10–14
c
0.2 0.8 1.4 —
Propagation Delay
Difference Between
Any 2 Parts
t
PLH
–
t
PHL
–0.4 0.3 0.9 μs T
A
= 25°C Pulse: f = 10 kHz, Duty Cycle = 50%
I
F
= 12 mA, V
CC
= 15.0V
R
L
= 20 k, C
L
= 100 pF
V
THHL
= 1.5V, V
THLH
= 2.0V
6, 10–14
d
d. The difference between t
PLH
and t
PHL
, between any two ACPL-W454/P454 parts under the same test condition. (See Power Inverter Dead Time and
Propagation Delay Specifications section).
–0.7 0.3 1.3 μs —
Common Mode
Transient Immunity at
Logic High Level
Output
|CM
H
| 15 30 — kV/s T
A
= 25°C V
CC
= 5.0V, R
L
= 1.9 k
C
L
= 15 pF, I
F
= 0 mA, V
CM
= 1500 V
P-P
7
b, e
e. Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dV
CM
/dt on the leading
edge of the common mode pulse, V
CM
, to assure that the output will remain in a Logic High state (that is, V
O
> 2.0V). Common mode transient immunity in a
Logic Low level is the maximum tolerable (negative) dV
CM
/dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will
remain in a Logic Low state (that is, VO < 0.8V).
15 30 — T
A
= 25°C V
CC
= 15.0V, R
L
= 20 k
C
L
= 100 pF, I
F
= 0 mA
V
CM
= 1500 V
P-P
7
c, f
f. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable
dV
CM
/dt on the leading edge of the common mode pulse, V
CM
, to assure that the output will remain in a Logic High state (that is, V
O
> 3.0V). Common mode
transient immunity in a Logic Low level is the maximum tolerable dV
CM
/dt on the trailing edge of the common mode pulse signal, V
CM
, to assure that the
output will remain in a Logic Low state that is, V
O
< 1.0V).
Common Mode
Transient Immunity at
Logic Low Level
Output
|CM
L
| 15 30 — kV/μs T
A
= 25°C V
CC
= 5.0V, R
L
= 1.9 k
C
L
= 15 pF, I
F
= 16 mA
V
CM
= 1500 V
P-P
7
b, e
15 30 — T
A
= 25°C V
CC
= 15.0V, R
L
= 20 k
C
L
= 100 pF, I
F
= 12 mA
V
CM
= 1500 V
P-P
7
c, f
15 30 — T
A
= 25°C V
CC
= 15.0V, R
L
= 20 k
C
L
= 100 pF, I
F
= 16 mA
V
CM
= 1500 V
P-P
7
c, f