CY7B9945V RoboClock
®
Document Number: 38-07336 Rev. *N Page 10 of 18
Capacitance
Parameter Description Test Conditions Min Max Unit
C
IN
Input Capacitance T
A
= 25 °C, f = 1 MHz, V
CC
= 3.3 V 5 pF
Thermal Resistance
Parameter
[6]
Description Test Conditions 52-pin TQFP Unit
θ
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
55 °C/W
θ
JC
Thermal resistance
(junction to case)
16 °C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
[7]
Notes
6. These parameters are guaranteed by design and are not tested.
7. Assumes 25 pF Maximum Load Capacitance up to 185 MHz. At 200 MHz the maximum load is 10 pF.
CY7B9945V RoboClock
®
Document Number: 38-07336 Rev. *N Page 11 of 18
Switching Characteristics
Over the Operating Range
[8, 9, 10, 11, 12]
Parameter Description
CY7B9945V-2 CY7B9945V-5
Unit
Min Max Min Max
f
in
Clock Input Frequency 24 200 24 200 MHz
f
out
Clock Output Frequency 24 200 24 200 MHz
t
SKEWPR
Matched Pair Skew
[13, 14]
, 1Q[0:1], 1Q[2:3], 2Q[0:1],
2Q[2:3], 2Q[4:5]
200 200 ps
t
SKEWBNK
Intrabank Skew
[13, 14]
250 250 ps
t
SKEW0
Output-Output Skew (same frequency and phase,
rise to rise, fall to fall)
[13, 14]
250 550 ps
t
SKEW1
Output-Output Skew (same frequency and phase,
other banks at different frequency,
rise to rise, fall to fall)
[13, 14]
250 650 ps
t
SKEW2
Output-Output Skew
(all output configurations
outside of t
SKEW0
and t
SKEW1
)
[12, 15]
500 800 ps
t
CCJ1-3
Cycle-to-Cycle Jitter (divide by 1 output frequency,
FB = divide by 1, 2, 3)
150 150 ps
Peak-
Peak
t
CCJ4-12
Cycle-to-Cycle Jitter (divide by 1 output frequency,
FB = divide by 4, 5, 6, 8, 10, 12)
100 100 ps
Peak-
Peak
t
PD
Propagation Delay, REF to FB Rise –250 250 –500 500 ps
TTB Total Timing Budget window
(same frequency and phase)
[16, 17]
500 700 ps
t
PDDELTA
Propagation Delay difference between two devices
[18]
200 200 ps
t
REFpwh
REF input (Pulse Width HIGH)
[8]
2.0 2.0 ns
t
REFpwl
REF input (Pulse Width LOW)
[8]
2.0 2.0 ns
Notes
8. This is for non-three level inputs.
9. Both outputs of pair must be terminated, even if only one is being used.
10. Each package must be properly decoupled.
11. AC parameters are measured at 1.5 V, unless otherwise indicated.
12. Test Load C
L
= 25 pF, terminated to V
CC
/2 with 50up to185 MHz and 10 pF load to 200 MHz.
13. Tested initially and after any design or process changes that affect these parameters.
14. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,
operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle
jitter, and dynamic phase error. TTB is equal to or smaller than the maximum specified value at a given output frequency.
15. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all
outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.
16. Guaranteed by statistical correlation. Tested initially and after any design or process changes that affects these parameters.
17. Rise and fall times are measured between 2.0 V and 0.8 V.
18. f
NOM
must be within the frequency range defined by the same FS state.
CY7B9945V RoboClock
®
Document Number: 38-07336 Rev. *N Page 12 of 18
t
r
/t
f
Output Rise/Fall Time
[19]
0.15 2.0 0.15 2.0 ns
t
LOCK
PLL Lock TIme From Power Up 10 10 ms
t
RELOCK1
PLL Relock Time (from same frequency, different phase)
with Stable Power Supply
500 500 s
t
RELOCK2
PLL Re-lock Time (from different frequency, different
phase) with Stable Power Supply
[20]
1000 1000 s
t
ODCV
Output duty cycle deviation from 50%
[21]
–1.0 1.0 –1.0 1.0 ns
t
PWH
Output HIGH time deviation from 50%
[22]
1.5 1.5 ns
t
PWL
Output LOW time deviation from 50%
[22]
2.0 2.0 ns
t
PDEV
Period deviation when changing
from reference to reference
[23]
0.025 0.025 UI
t
OAZ
DIS[1:2] HIGH to output high-impedance
from ACTIVE
[24, 25]
1.0 10 1.0 10 ns
t
OZA
DIS[1:2] LOW to output ACTIVE from output is high
impedance
[25]
0.5 14 0.5 14 ns
Switching Characteristics (continued)
Over the Operating Range
[8, 9, 10, 11, 12]
Parameter Description
CY7B9945V-2 CY7B9945V-5
Unit
Min Max Min Max
Notes
19. t
PWH
is measured at 2.0 V. t
PWL
is measured at 0.8 V.
20. f
NOM
must be within the frequency range defined by the same FS state.
21. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all
outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.
22. Measured at 0.5 V deviation from starting voltage.
23. For t
OZA
minimum, C
L
= 0 pF. For t
OZA
maximum, C
L
= 25 pF to 185 MHz or 10 pF to 200 MHz.
24. Tested initially and after any design or process changes that affect these parameters.
25. These figures are for illustration purposes only. The actual ATE loads may vary.

CY7B9945V-5AXCT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL 3.3V 200MHz 10 COM Programable
Lifecycle:
New from this manufacturer.
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