MAX811/MAX812
4-Pin µP Voltage Monitors
with Manual Reset Input
_______________________________________________________________________________________ 5
______________________________________________________________ Pin Description
_______________ Detailed Description
Reset Output
A microprocessor’s (µP’s) reset input starts the µP in a
known state. These µP supervisory circuits assert reset
to prevent code execution errors during power-up,
power-down, or brownout conditions.
RESET is guaranteed to be a logic low for V
CC
> 1V.
Once V
CC
exceeds the reset threshold, an internal
timer keeps RESET low for the reset timeout period;
after this interval, RESET goes high.
If a brownout condition occurs (V
CC
dips below the
reset threshold), RESET goes low. Any time V
CC
goes
below the reset threshold, the internal timer resets to
zero, and RESET goes low. The internal timer starts
after V
CC
returns above the reset threshold, and RESET
remains low for the reset timeout period.
The manual reset input (MR) can also initiate a reset.
See the
Manual Reset Input
section.
The MAX812 has an active-high RESET output that is
the inverse of the MAX811’s RESET output.
Manual Reset Input
Many µP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic low on MR
asserts reset. Reset remains asserted while MR is low,
and for the Reset Active Timeout Period (t
RP
) after MR
returns high. This input has an internal 20kΩ pull-up
resistor, so it can be left open if it is not used. MR can
be driven with TTL or CMOS-logic levels, or with open-
drain/collector outputs. Connect a normally open
momentary switch from MR to GND to create a manual-
reset function; external debounce circuitry is not
required. If MR is driven from long cables or if the
device is used in a noisy environment, connecting a
0.1µF capacitor from MR to ground provides additional
noise immunity.
Reset Threshold Accuracy
The MAX811/MAX812 are ideal for systems using a 5V
±5% or 3V ±5% power supply with ICs specified for 5V
±10% or 3V ±10%, respectively. They are designed to
meet worst-case specifications over temperature. The
reset is guaranteed to assert after the power supply
falls out of regulation, but before power drops below
the minimum specified operating voltage range for the
system ICs. The thresholds are pre-trimmed and exhibit
tight distribution, reducing the range over which an
undesirable reset may occur.
Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as MR is
low and for 180ms after MR returns high. This active-low input has an internal 20kΩ pull-up
resistor. It can be driven from a TTL or CMOS-logic line, or shorted to ground with a switch.
Leave open if unused.
33
+5V, +3.3V, or +3V Supply Voltage44
Active-High Reset Output. RESET remains high while V
CC
is below the reset threshold or while
MR is held low. RESET remains high for Reset Active Timeout Period (t
RP
) after the reset condi-
tions are terminated.
2—
Active-Low Reset Output. RESET remains low while V
CC
is below the reset threshold or while
MR is held low. RESET remains low for the Reset Active Timeout Period (t
RP
) after the reset
conditions are terminated.
—2
Ground
11
FUNCTION
PIN
MR
V
CC
RESET
RESET
GND
NAME
MAX811 MAX812
