AD676
REV. A
–12–
AD586 output, thereby optimizing the overall performance of
the AD676. It is recommended that a 10 µF to 47 µF high qual-
ity tantalum capacitor be tied between the V
REF
input of the
AD676 and ground to minimize the impedance on the
reference.
+15V
+5V
–15V
100µF
100µF
100µF
AD676
10µF
10µF
0.1µF
0.1µF
0.1µF
78L12
79L12
0.01µF
0.01µF
V
REF
V
DD
V
CC
V
EE
V
IN
V
O
NR
GND
10µF
0.1µF
1µF
AD587
10µF
1517
18
12
16
4
2
6
8
V
IN
V
IN
10
10
10
10
Figure 7.
Using the AD676 with ±10 V input range (V
REF
= 10 V) typi-
cally requires ±15 V supplies to drive op amps and the voltage
reference. If ±12 V is not available in the system, regulators
such as 78L12 and 79L12 can be used to provide power for the
AD676. This is also the recommended approach (for any input
range) when the ADC system is subjected to harsh environ-
ments such as where the power supplies are noisy and where
voltage spikes are present. Figure 7 shows an example of such a
system based upon the 10 V AD587 reference, which provides a
300 µV LSB. Circuitry for additional protection against power
supply disturbances has been shown. A 100 µF capacitor at each
regulator prevents very large voltage spikes from entering the
regulators. Any power line noise which the regulators cannot
eliminate will be further filtered by an RC filter (10 /10 µF)
having a –3 dB point at 1.6 kHz. For best results the regulators
should be within a few centimeters of the AD676.
ANALOG INPUT
As previously discussed, the analog input voltage range for the
AD676 is ±V
REF
. For purposes of ground drop and common
mode rejection, the V
IN
and V
REF
inputs each have their own
ground. V
REF
is referred to the local analog system ground
(AGND), and V
IN
is referred to the analog ground sense pin
(AGND SENSE) which allows a remote ground sense for the
input signal.
The AD676 analog inputs (V
IN
, V
REF
and AGND SENSE) ex-
hibit dynamic characteristics. When a conversion cycle begins,
each analog input is connected to an internal, discharged 50 pF
capacitor which then charges to the voltage present at the corre-
sponding pin. The capacitor is disconnected when SAMPLE is
taken LOW, and the stored charge is used in the subsequent
conversion. In order to limit the demands placed on the external
source by this high initial charging current, an internal buffer
amplifier is employed between the input and this capacitance for
a few hundred nanoseconds. During this time the input pin ex-
hibits typically 20 k input resistance, 10 pF input capacitance
and ±40 µA bias current. Next, the input is switched directly to
the now precharged capacitor and allowed to fully settle. During
this time the input sees only a 50 pF capacitor. Once the sample
is taken, the input is internally floated so that the external input
source sees a very high input resistance and a parasitic input ca-
pacitance of typically only 2 pF. As a result, the only dominant
input characteristic which must be considered is the high cur-
rent steps which occur when the internal buffers are switched in
and out.
In most cases, these characteristics require the use of an external
op amp to drive the input of the AD676. Care should he taken
with op amp selection; even with modest loading conditions,
most available op amps do not meet the low distortion require-
ments necessary to match the performance capabilities of the
AD676. Figure 8 represents a circuit, based upon the AD845,
recommended for low noise, low distortion ac applications.
For applications optimized more for low bias and low offset than
speed or bandwidth, the AD845 of Figure 8 may be replaced by
the OP27.
499
1k
+12V
–12V
AD845
0.1µF
0.1µF
AGND
AGND
SENSE
±5V
INPUT
1k
AD676
15
13
14
2
3
4
7
6
V
IN
Figure 8.
AD676
REV. A
–13–
AC PERFORMANCE
AC parameters, which include S/(N+D), THD, etc., reflect the
AD676’s effect on the spectral content of the analog input sig-
nal. Figures 12 through 16 provide information on the AD676’s
ac performance under a variety of conditions.
As a general rule, averaging the results from several conversions
reduces the effects of noise, and therefore improves such param-
eters as S/(N+D). AD676 performance may be optimized by
operating the device at its maximum sample rate of 100 kSPS
and digitally filtering the resulting bit stream to the desired signal
bandwidth. This succeeds in distributing noise over a wider
frequency range, thus reducing the noise density in the fre-
quency band of interest. This subject is discussed in the follow-
ing section.
OVERSAMPLING AND NOISE FILTERING
The Nyquist rate for a converter is defined as one-half its sam-
pling rate. This is established by the Nyquist theorem, which re-
quires that a signal he sampled at a rate corresponding to at
least twice its highest frequency component of interest in order
to preserve the informational content. Oversampling is a conver-
sion technique in which the sampling frequency is more than
twice the frequency bandwidth of interest. In audio applications,
the AD676 can operate at a 2 3 F
S
oversampling rate, where
F
S
= 48 kHz.
In quantized systems, the informational content of the analog
input is represented in the frequency spectrum from dc to the
Nyquist rate of the converter. Within this same spectrum are
higher frequency noise and signal components. Antialias, or low
pass, filters are used at the input to the ADC to reduce these
noise and signal components so that their aliased components
do not corrupt the baseband spectrum. However, wideband
noise contributed by the AD676 will not be reduced by the
antialias filter. The AD676 quantization noise is evenly distrib-
uted from dc to the Nyquist rate, and this fact can be used to
minimize its overall affect.
The AD676 quantization noise effects can be reduced by
oversampling–sampling at a rate higher than that defined by the
Nyquist theorem. This spreads the noise energy over a band-
width wider than the frequency band of interest. By judicious
selection of a digital decimation filter, noise frequencies outside
the bandwidth of interest may be eliminated.
The process of analog to digital conversion inherently produces
noise, known as quantization noise. The magnitude of this noise
is a function of the resolution of the converter, and manifests it-
self as a limit to the theoretical signal-to-noise ratio achievable.
This limit is described by S/(N+D) = (6.02n + 1.76 + 10 log
F
S
/2F
A
) dB, where n is the resolution of the converter in bits, F
S
is the sampling frequency, and Fa is the signal bandwidth of in-
terest. For audio bandwidth applications, the AD676 is capable
of operating at a 2 3 oversample rate (96 kSPS), which typically
produces an improvement in S/(N+D) of 3 dB compared with
operating at the Nyquist conversion rate of 48 kSPS. Over-
sampling has another advantage as well; the demands on the
antialias filter are lessened. In summary, system performance is
optimized by running the AD676 at or near its maximum sam-
pling rate of 100 kHz and digitally filtering the resulting spec-
trum to eliminate undesired frequencies.
DC CODE UNCERTAINTY
Ideally, a fixed dc input should result in the same output code
for repetitive conversions. However, as a consequence of system
noise and circuit noise, for a given input voltage there is a range
of output codes which may occur. Figure 9 is a histogram of the
codes resulting from 1000 conversions of a typical input voltage
by the AD676 used with a 10 V reference.
2
10–1
DEVIATION FROM CORRECT CODE – LSBs
NUMBER OF CODE HITS
800
0
200
400
600
Figure 9. Distribution of Codes from 1000 Conversions,
Relative to the Correct Code
The standard deviation of this distribution is approximately 0.5
LSBs. If less uncertainty is desired, averaging multiple conver-
sions will narrow this distribution by the inverse of the square
root of the number of samples; i.e., the average of 4 conversions
would have a standard deviation of 0.25 LSBs.
AD676
REV. A
–14–
MICROPROCESSOR INTERFACE
The AD676 is ideally suited for use in both traditional dc mea-
surement applications supporting a microprocessor, and in ac
signal processing applications interfacing to a digital signal pro-
cessor. The AD676 is designed to interface with a 16-bit data
bus, providing all output data bits in a single read cycle. A vari-
ety of external buffers, such as 74HC541, can be used with the
AD676 to provide 3-state outputs, high driving capability, and
to prevent bus noise from coupling into the ADC. The following
sections illustrate the use of the AD676 with a representative
digital signal processor and microprocessor. These circuits pro-
vide general interface practices which are applicable to other
processor choices.
ADSP-2101
Figure 10a shows the AD676 interfaced to the ADSP-2101 DSP
processor. The AD676 buffers are mapped in the ADSP-2101’s
memory space, requiring one wait state when using a 12.5 MHz
processor clock.
The falling edge of BUSY interrupts the processor, indicating
that new data is ready. The ADSP-2101 automatically jumps to
the appropriate service routine with minimal overhead. The in-
terrupt routine then instructs the processor to read the new data
using a memory read instruction.
A0
A13
D8 – D23
ADSP-2101
IRQ2
RD
DMS
DECODER
CS
ADDRESS BUS
Y1 – Y8
A1 – A3
74HC541
G1
G2
Y1 – Y8
A1 – A3
74HC541
G1
G2
BUSY
BIT 1 – BIT 16
AD676
16
8
8
8
16
8
Figure 10a.
Figure 10b shows circuitry which would be included by a typical
address decoder for the output buffers. In this case, a data
memory access to any address in the range 3000H to 37FFH
will result in the output buffers being enabled.
The AD676 CLK and SAMPLE can be generated by dividing
down the system clock as described earlier (Figure 3), or if the
ADSP-2101 serial port clocks are not being used, they can be
programmed to generate CLK and SAMPLE.
A13
A12
A11
DMS
CS
Figure 10b.
80286
The 80286 16-bit microprocessor can be interfaced to a buff-
ered AD676 without any generation of wait states. As seen in
Figure 11, BUSY can be used both to control the AD676 clock
and to alert the processor when new data is ready. In the system
shown, the 80286 should be configured in an edge triggered, di-
rect interrupt mode (integrated controller provides the interrupt
vector). Since the 80286 does not latch interrupt signals, the in-
terrupt needs to be internally acknowledged before BUSY goes
HIGH again during the next AD676 conversion (BUSY = 0).
Depending on whether the AD676 buffers are mapped into
memory or 1/0 space, the interrupt service routine will read the
data by using either the MOV or the IN instruction. To be able
to read all the 16 bits at once, and thereby increase the 80286’s
efficiency, the buffers should be located at an even address.
AD0 – AD15
ALE
CLKOUT
INT 0
80286
RD
PCSO – 6
S2
DECODER
CS
16
Y1 – Y8
A1 – A8
74HC541
G1
G2
Y1 – Y8
A1 – A8
74HC541
G1
G2
8
8
DIVIDER
D
CLR
Q
Q
D
CLR
Q
Q
74HC04
74HC74
BIT1 – BIT16
SAMPLE
CLK
BUSY
AD676
2MHz
16
8
8
Figure 11.

AD676BD

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit Parallel 100 kSPS Sampling
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union