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74ACT533SCX

P1-P3P4-P6P7-P7
© 2005 Fairchild Semiconductor Corporation DS500311 www.fairchildsemi.com
August 1999
Revised March 2005
74ACT533 Octal Transparent Latch with 3-STATE Outputs
74ACT533
Octal Transparent Latch with 3-STATE Outputs
General Description
The ACT533 consists of eight latches with 3-STATE out-
puts for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is low, the data satisfying the input timing
requirements is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
Features
■ I
CC
and I
OZ
reduced by 50%
■ Eight latches in a single package
■ 3-STATE outputs drive bus lines or buffer memory
address registers
■ Outputs source/sink 24 mA
■ Inverted version of the ACT373
■ TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACT533SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT533MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT533PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names Description
D
0
–D
7
Data Inputs
LE Latch Enable Input
OE
Output Enable Input
O
0
–O
7
3-STATE Latch Outputs
www.fairchildsemi.com 2
74ACT533
Functional Description
The ACT533 contains eight D-type latches with 3-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the D
n
inputs enters the latches. In this con-
dition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs at setup time preceding the HIGH-to-LOW
transition of LE. The 3-STATE standard outputs are con-
trolled by the Output Enable (OE
) input. When OE is LOW,
the standard outputs are in the 2-state mode. When OE
is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the latches.
Truth Table
H HIGH Voltage Level
L
LOW Voltage Level
Z
High Impedance
X
Immaterial
O
0
Previous O
0
before HIGH-to-LOW transition of Latch Enable
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs Outputs
LE OE
D
n
O
n
X H X Z
H L L H
H L H L
L L X O
0
3 www.fairchildsemi.com
74ACT533
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
circuits outside databook specifications.
DC Electrical Characteristics
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Supply Voltage (V
CC
) 0.5V to 7.0V
DC Input Diode Current (I
IK
)
V
I
0.5V 20 mA
V
I
V
CC
0.5V 20 mA
DC Input Voltage (V
I
) 0.5V to V
CC
0.5V
DC Output Diode Current (I
OK
)
V
O
0.5V 20 mA
V
O
V
CC
0.5V 20 mA
DC Output Voltage (V
O
) 0.5V to V
CC
0.5V
DC Output Source
or Sink Current (I
O
) 50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) 50 mA
Storage Temperature (T
STG
) 65 C to 150 C
DC Latchup Source
or Sink Current
300 mA
Junction Temperature (T
J
)
PDIP 140
C
Supply Voltage (V
CC
) 4.5V to 5.5V
Input Voltage (V
I
) 0V to V
CC
Output Voltage (V
O
) 0V to V
CC
Operating Temperature (T
A
) 40 C to 85 C
Minimum Input Edge Rate
V/ t
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V 125 mV/ns
Symbol Parameter
V
CC
T
A
25 C T
A
40 C to 85 C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 4.5 1.5 2.0 2.0
V
V
OUT
0.1V
Input Voltage 5.5 1.5 2.0 2.0 or V
CC
0.1V
V
IL
Maximum LOW Level 4.5 1.5 0.8 0.8
V
V
OUT
0.1V
Input Voltage 5.5 1.5 0.8 0.8 or V
CC
0.1V
V
OH
Minimum HIGH Level 4.5 4.49 4.4 4.4
V
I
OUT
50 A
Output Voltage 5.5 5.49 5.4 5.4
V
IN
V
IL
or V
IH
4.5 3.86 3.76 V I
OH
24 mA
5.5 4.86 4.76 I
OH
24 mA (Note 2)
V
OL
Maximum LOW Level 4.5 0.001 0.1 0.1
V
I
OUT
50 A
Output Voltage 5.5 0.001 0.1 0.1
V
IN
V
IL
or V
IH
4.5 0.36 0.44 V I
OL
24 mA
5.5 0.36 0.44 I
OL
24 mA (Note 2)
I
IN
Maximum Input 5.5 0.1 1.0 A V
I
V
CC
, GND
Leakage Current
I
OZ
Maximum 3-STATE
5.5 0.25 2.5 A
V
I
V
IL
, V
IH
Leakage Current V
O
V
CC
, GND
I
CCT
Maximum 5.5 0.6 1.5 mA V
I
V
CC
2.1V
I
CC
/Input
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
1.65V Max
I
OHD
Output Current (Note 3) 5.5 75 mA V
OHD
3.85V Min
I
CC
Maximum Quiescent
5.5 4.0 40.0 A
V
IN
V
CC
Supply Current or GND
P1-P3P4-P6P7-P7

74ACT533SCX

Mfr. #:
Buy 74ACT533SCX
Manufacturer:
ON Semiconductor / Fairchild
Description:
Latches Octal Trans Latch
Lifecycle:
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