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TAR5S50TE85LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
TAR5S15~TAR5S50
2007-11-01
4
Output Voltage Accuracy
(
V
IN
=
V
OUT
+
1 V, I
OUT
=
50 mA, C
IN
=
1
μ
F, C
OUT
=
10
μ
F, C
NOISE
=
0.01
μ
F, T
j
=
25°C)
Product No. Symbol Min Typ. Max Unit
TAR5S15 1.44 1.5 1.56
TAR5S16 1.54 1.6 1.66
TAR5S17 1.64 1.7 1.76
TAR5S18 1.74 1.8 1.86
TAR5S19 1.84 1.9 1.96
TAR5S20 1.94 2.0 2.06
TAR5S21 2.04 2.1 2.16
TAR5S22 2.14 2.2 2.26
TAR5S23 2.24 2.3 2.36
TAR5S24 2.34 2.4 2.46
TAR5S25 2.43 2.5 2.57
TAR5S26 2.53 2.6 2.67
TAR5S27 2.63 2.7 2.77
TAR5S28 2.73 2.8 2.87
TAR5S29 2.83 2.9 2.97
TAR5S30 2.92 3.0 3.08
TAR5S31 3.02 3.1 3.18
TAR5S32 3.12 3.2 3.28
TAR5S33 3.21 3.3 3.39
TAR5S34 3.31 3.4 3.49
TAR5S35 3.41 3.5 3.59
TAR5S36 3.51 3.6 3.69
TAR5S37 3.6 3.7 3.8
TAR5S38 3.7 3.8 3.9
TAR5S39 3.8 3.9 4.0
TAR5S40 3.9 4.0 4.1
TAR5S41 3.99 4.1 4.21
TAR5S42 4.09 4.2 4.31
TAR5S43 4.19 4.3 4.41
TAR5S44 4.29 4.4 4.51
TAR5S45 4.38 4.5 4.62
TAR5S46 4.48 4.6 4.72
TAR5S47 4.58 4.7 4.82
TAR5S48 4.68 4.8 4.92
TAR5S49 4.77 4.9 5.03
TAR5S50
V
OUT
4.87 5.0 5.13
V
TAR5S15~TAR5S50
2007-11-01
5
Application Note
1. Recommended Application Circuit
The figure above shows the recommended configuration for using a point regulator. Insert a capacitor for
stable input/output operation. If the control function is not to be used, Toshiba recommend that the control pin
(pin 1) be connected to the V
CC
pin.
2. Power Dissipation
The power dissipation for board-mounted TAR5Sxx Series devices (rated at 380 mW) is measured using a
board whose size and pattern are as shown below. When incorporating a device belonging to this series into
your design, derate the power dissipation as far as possible by reducing the levels of parameters such as input
voltage, output current and ambient temperature. Toshiba recommend that these devices should typically be
derated to 70%~80% of their absolute maximum power dissipation value.
Thermal Resistance Evaluation Board
Circuit board material: glass epoxy,
Circuit board dimension:30 mm × 30 mm,
Copper foil pad area: 50 mm
2
(t = 0.8 mm)
C
OUT
C
IN
C
NOISE
V
IN
V
OUT
CONTROL GND NOISE
V
IN
5
NOISE
4
1 3
GND
2
V
OUT
CONTROL
0.01 μF
1 μF
10 μF
Control Level Operation
HIGH ON
LOW OFF
TAR5S15~TAR5S50
2007-11-01
6
3. Ripple Rejection
The devices of the TAR5Sxx Series feature a circuit with an excellent ripple rejection characteristic. Because
the circuit also features an excellent output fluctuation characteristic for sudden supply voltage drops, the
circuit is ideal for use in the RF blocks incorporated in all mobile telephones.
4. NOISE Pin
TAR5Sxx Series devices incorporate a NOISE pin to reduce output noise voltage. Inserting a capacitor
between the NOISE pin and GND reduces output noise. To ensure stable operation, insert a capacitor of
0.0047 μF or more between the NOISE pin and GND.
The output voltage rise time varies according to the capacitance of the capacitor connected to the NOISE
pin.
Ripple Rejection − f
TAR5S28 Input Transient Response
Frequency f (Hz)
Time t (ms)
Ripple rejection (dB)
0
10 100 1 k 10 k 100 k 300 k
10
20
30
40
50
60
70
80
10 μF
2.2 μF
1 μF
V
IN
= 4.0 V, C
NOISE
= 0.01 μF,
C
IN
= 1 μF, V
ripple
= 500 mV
p
−
p
,
I
out
= 10 mA, Ta = 25°C
C
NOISE
− V
N
Turn On Waveform
NOISE capacitance C
NOISE
(F)
Time t (ms)
Control voltage
V
CT (ON)
(V)
Output noise voltage V
N
(μV)
0
10
20
30
40
50
60
0.001 μ 0.01 μ 1.0 μ
TAR5S50
0.1 μ
TAR5S30
TAR5S15
C
IN
= 1 μF, C
out
= 10 μF,
I
out
= 10 mA, Ta = 25°C
Output voltage
V
OUT
(V)
01 45 8 10
Input voltage
2.8 V
2 3 6 7 9
Output voltage
3.1 V
3.4 V
Ta = 25°C, C
IN
= 1 μF,
C
out
= 10 μF, C
NOISE
= 0.01 μF,
V
IN
: 3.4 V → 3.1 V, I
out
= 50 mA
4010 20
0
1
2
3
1
2
−10 0 9030
0
60 50 80 70
Output voltage waveform
Control voltage waveform
C
NOISE
= 0.01 μF
1 μF
0.33 μF
0.1 μF
C
IN
= 1 μF, C
out
= 10 μF,
I
out
= 50 mA, Ta = 25°C
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

TAR5S50TE85LF

Mfr. #:
Buy TAR5S50TE85LF
Manufacturer:
Toshiba
Description:
LDO Voltage Regulators Point Reg SGL output 200mA 15V 5V out
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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