LTC1257CS8#PBF

LTC1257
4
1257fc
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current
vs Logic Input Voltage Output Swing vs Load Resistance
Pull-Down Voltage
vs Output Sink Current Capability
Minimum Supply Voltage
vs Load Current #1
Minimum Supply Voltage
vs Load Current #2 Supply Current vs Temperature
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= T
MIN
to T
MAX
. V
CC
= 4.75V to 15.75V, internal or external reference
(2.475V ≤ V
REF
≤ V
CC
– 2.7V), unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
5
LOAD Pulse Width
l
150 ns
t
6
LSB CLK to LOAD
l
0 ns
t
7
LOAD High to CLK
l
0 ns
t
8
D
OUT
Output Delay C
LOAD
= 15pF
l
35 150 ns
f
CLK
Maximum Clock Frequency 1.4 MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
Guaranteed by design; not subject to test.
Note 3: DAC switched from all 1s to all 0s, and all 0s to all 1s code.
Note 4: Guaranteed with internal V
REF
or with external V
REF
range of
2.475V to 12V. Tested at 10V.
OUTPUT LOAD CURRENT (mA)
0.01
MINIMUM SUPPLY VOLTAGE (V)
0.1 1 10
1257 G01
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
V
REF
= INTERNAL
V
OUT
= FULL SCALE
T
A
= 25°C
OUTPUT LOAD CURRENT (mA)
0.01
MINIMUM SUPPLY VOLTAGE (V)
0.1 1 10
1257 G02
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
V
REF
= 10V
V
OUT
= FULL SCALE
T
A
= 25°C
TEMPERATURE (°C)
50
0.38
0.37
0.36
0.35
0.34
0.33
0.32
0.31
25 75
1257 G03
25 0
50 100 125
SUPPLY CURRENT (mA)
V
CC
= 5.25V
V
CC
= 5V
V
CC
= 4.75V
LOGIC VOLTAGE (V)
0
SUPPLY CURRENT (mA)
0.59
0.54
0.49
0.44
0.39
0.34
4
1257 G04
1
2
3
5
V
CC
= 5V
T
A
= 25°C
LOAD RESISTANCE (Ω)
10
OUTPUT VOLTAGE SWING (V)
100 1k 10k
1257 G05
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
FULL SCALE
R
L
TIED TO GND
ZERO SCALE
R
L
TIED TO V
CC
V
CC
= 5V
OUTPUT SINK CURRENT (µA)
1
OUTPUT PULL-DOWN VOLTAGE (mV)
1000
100
10
1
0.1
10 100 1000
1257 G06
HOT
COLD
ROOM
LTC1257
5
1257fc
TYPICAL PERFORMANCE CHARACTERISTICS
Differential Nonlinearity (DNL)
Reference Compensation
Resistance vs C
L
Broadband Noise
Full-Scale Voltage
vs Temperature
Zero-Scale Voltage
vs Temperature Integral Nonlinearity (INL)
TEMPERATURE (°C)
50
FULL-SCALE VOLTAGE (V)
2.0495
2.0490
2.0485
2.0480
2.0475
2.0470
2.0465
25 75
1257 G07
25 0
50 100 125
V
CC
= 5V
INTERNAL REFERENCE
TEMPERATURE (°C)
50 25 25 50
ZERO-SCALE VOLTAGE (mV)
75 100
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1257 G08
0 125
V
CC
= 5V
INTERNAL REFERENCE
CODE
0
ERROR (LSB)
2.0
1.6
1.2
0.8
0.4
0
0.4
0.8
1.2
1.6
2.0
1024
2048
2560
1257 G09
512 1536
3072
3584
4096
V
CC
= 5V
INTERNAL REFERENCE
T
A
= 25°C
CODE
0
DNL ERROR (LSBs)
0.5
0.0
0.5
1024 2048 2560
1257 TA05
512 1536 3072 3584
4098
C
L
(µF)
0.01
REFERENCE COMPENSATION RESISTANCE (Ω)
70
60
50
40
30
20
10
0
0.1 1
1257 G11
10 100
TIME = 5ms/DIV
0.1V/DIV
1257 G12
CODE = FFF
H
BW = 3Hz TO 1MHz
GAIN = 1100×
PIN FUNCTIONS
CLK (Pin 1): The TTL level input for the serial interface clock.
D
IN
(Pin 2): The TTL level input for the serial interface
data. Data on the D
IN
pin is latched into the shift register
on the rising edge of the serial clock.
LOAD (Pin 3): The TTL level input for the serial interface
load control. Data is loaded from the shift register into the
DAC
register, thus updating the DAC output when LOAD
is pulled low. The DAC register is transparent as long as
LOAD is held low.
D
OUT
(Pin 4): The output of the shift register which becomes
valid on the rising edge of the serial clock. The D
OUT
pin
is driven from GND to V
CC
by an internal CMOS inverter.
Multiple LTC1257s may be cascaded by connecting the
D
OUT
pin to the D
IN
pin of the next chip.
GND (Pin 5): Ground.
REF (Pin 6): The output of the 2.048V reference and the
input to the DAC resistor ladder. An external reference
with voltage from 2.475V to V
CC
– 2.7V may be used to
override the internal reference.
LTC1257
6
1257fc
PIN FUNCTIONS
DEFINITIONS
V
OUT
(Pin 7): The buffered DAC output is capable of
sourcing 2mA over temperature while pulling within 2.7V
of V
CC
. The output will pull to ground through an internal
250Ω equivalent resistance.
V
CC
(Pin 8): The positive supply input. 4.75VV
CC
15.75V. Requires a bypass capacitor to ground.
LSB: The least significant bit or the ideal voltage difference
between two successive codes.
LSB
= (V
FS
– V
OS
)/2
n
– 1
n
= The number of digital input bits
V
OS
= The zero code error or offset of the DAC
V
FS
= The full-scale output voltage of the DAC
measured when all bits are set to 1
Resolution: The resolution is the number of DAC output
states (2
n
) that divide the full-scale range. The resolution
does not imply linearity.
INL: End-point integral nonlinearity is the maximum devia-
tion from a straight line passing through the end-points of
the DAC transfer curve. Because the part
operates from
a single supply and the output cannot go below ground,
the linearity is measured between full-scale and the first
code that guarantees a positive output. The INL error at
a given input code is calculated as follows:
INL
= (V
OUT
– V
IDEAL
)/LSB
V
IDEAL
= (Code)(LSB) + V
OS
V
OUT
= The output voltage of the DAC measured at
the given input code
DNL: Differential nonlinearity is the difference between
the measured change and the ideal 1LSB change between
any two adjacent codes. The DNL error between any two
codes is calculated as follows:
DNL
= (∆V
OUT
– LSB)/LSB
∆V
OUT
= The measured voltage difference between two
adjacent codes
Offset Error: The theoretical voltage at the output when
the DAC is loaded with all zeros. The output amplifier can
have a true negative offset, but because the part is oper-
ated from a single supply, the output cannot go below
ground. If the offset is negative, the output will remain
near 0V resulting in the transfer curve shown
in Figure 1.
The offset of the part is measured at the first code that
produces an output voltage 0.5LSB greater than the
previous code:
V
OS
= V
OUT
– [(Code)(V
FS
)/(2
n
– 1)]
Full-Scale Error: Full-scale error is the difference between
the ideal and measured DAC output voltages with all bits
set to one (Code = 4095). The full-scale error includes the
offset error and is calculated as follows:
FSE
= (V
OUT
– V
IDEAL
)/LSB
V
IDEAL
= (V
REF
)(1 – 2
–n
) – V
OS
V
REF
= The reference voltage, either internal or external
Gain Error: Gain error is the difference between the ideal
and measured slope of the DAC transfer characteristic.
Gain error is equal to full-scale error minus offset error.
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(
nV)(sec).
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
{
DAC CODE
0V
1257 F01
Figure 1. Effect of Negative Offset

LTC1257CS8#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 12-bit Vout DAC w/ Internal Reference
Lifecycle:
New from this manufacturer.
Delivery:
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