AD1853JRSZ Datasheet AD1853JRSZ, AD1853JRSZRL | P10-P12

REV. A

AD1853

–9–

Table III. Digital Timing

Min Units

CCH

CCLK HI Pulsewidth 40 ns

CCL

CCLK LOW Pulsewidth 40 ns

CSU

CDATA Setup Time 10 ns

CHD

CDATA Hold Time 10 ns

CLL

CLATCH LOW Pulsewidth 10 ns

CLH

CLATCH HI Pulsewidth 10 ns

SPI REGISTER DEFINITIONS

The SPI port allows flexible control of many chip parameters.

It is organized around three registers; a LEFT-CHANNEL

VOLUME register, a RIGHT-CHANNEL VOLUME register

and a CONTROL register. Each WRITE operation to the

AD1853 SPI control port requires 16 bits of serial data in

MSB-first format. The bottom two bits are used to select one

of three registers, and the top 14 bits are then written to that

single 16-bit transaction.

The SPI CCLK signal is used to clock in the data. The incom-

ing data should change on the falling edge of this signal. At the

end of the 16 CCLK periods, the CLATCH signal should rise

to latch the data internally into the AD1853.

The lowest two bits of the 16-bit input word are decoded as

follows to set the register into which the upper 14 bits will be

written.

Bit 1 Bit 0 Register

00Volume Left

10Volume Right

01Control Register

VOLUME LEFT and VOLUME RIGHT Registers

A write operation to the left or right volume registers will acti-

vate the “auto-ramp” clickless volume control feature of the

AD1853. This feature works as follows. The upper 10 bits of

the volume control word will be incremented or decremented by

1 at a rate equal to the input sample rate. The bottom 4 bits are

not fed into the auto-ramp circuit and thus take effect immedi-

ately. This arrangement gives a worst-case ramp time of about

1024/F

for step changes of more than 60 dB, which has been

determined by listening tests to be optimal in terms of pre-

venting the perception of a “click” sound on large volume

changes. See Figure 8 for a graphical description of how the

volume changes as a function of time.

The 14-bit volume control word is used to multiply the signal,

and therefore the control characteristic is linear, not dB. A con-

stant dB/step characteristic can be obtained by using a lookup

table in the microprocessor that is writing to the SPI port.

20ms

TIME

–60

LEVEL – dB

VOLUME REQUEST REGISTER

ACTUAL VOLUME REGISTER

Figure 8. Smooth Volume Control

REV. A

AD1853

–10–

Control Register

The following table shows the functions of the control register. The control register is addressed by having a “01” in the bottom 2 bits

of the 16-bit SPI word. The top 14 bits are then used for the control register.

Bit 11 Bit 10 Bit 9:8 Bit 7 Bit 6 Bit 5:4 Bit 3:2

INT2× Mode INT4× Mode Number of Soft Reset. Soft Mute OR’d Serial Mode OR’d De-Emphasis Filter

OR’d with Pin. OR’d with Pin. Bits in Right- Default = 0 with Pin. with Mode Pins. Select.

Default = 0 Default = 0 Justified Serial Default = 0 IDPMI:IDPM0 0:0 No Filter

Mode. 0:0 Right-Justified 0:1 44.1 kHz Filter

0:0 = 24 0:1 I

S 1:0 32 kHz Filter

0:1 = 20 1:0 Left-Justified 1:1 48 kHz Filter

1:0 = 16 1:1 DSP Mode Default = 0.0

Default = 0:0 Default = 0:0

Mute

The AD1853 offers two methods of muting the analog output.

By asserting the MUTE (Pin 23) signal HI, both the left and

right channel are muted. As an alternative, the user can assert

the mute bit in the serial control register (Bit 6) HI. The AD1853

has been designed to minimize pops and clicks when muting

and unmuting the device by automatically “ramping” the gain

up or down. When the device is unmuted, the volume returns to

the value set in the volume register.

Analog Attenuation

The AD1853 also offers the choice of using IREF (Pin 10) to

attenuate by up to 50 dB in the analog domain. This feature can

be used as an analog volume control. It is also a convenient

place to add a compressor/limiter gain control signal.

Output Drive, Buffering and Loading

The AD1853 analog output stage is able to drive a 1 kΩ (in

series with 2 nF) load. The analog outputs are usually ac

coupled with a 10 µF capacitor.

De-Emphasis

The AD1853 has a built-in de-emphasis filter that can be used

to decode CDs that have been encoded with the standard

“Redbook” 50 µs/15 µs emphasis response curve. Three curves

are available; one each for 32 kHz, 44.1 kHz and 48 kHz sam-

pling rates. The external “DEEMP” pin (Pin 9) turns on the

44.1 kHz de-emphasis filter. The other filters may be selected

by writing to control Bits 2 and 3 in the control register. If the

SPI port is used to control the de-emphasis filter, the external

DEEMP pin should be tied LO.

Control Signals

The IDPM0 and IDPM1 control inputs are normally con-

nected HI or LO to establish the operating state of the AD1853.

They can be changed dynamically (and asynchronously to

LRCLK and the master clock), but it is possible that a click

or pop sound may result during the transition from one serial

mode to another. If possible, the AD1853 should be placed in

mute before such a change is made.

Figures 9–14 show the calculated frequency response of the

digital interpolation filters. Figures 15–27 show the performance

of the AD1853 as measured by an Audio Precision System 2

Cascade. For the wideband plots, the noise floor shown in the

plots is higher than the actual noise floor of the AD1853. This is

caused by the higher noise floor of the “High Bandwidth” ADC

used in the Audio Precision measurement system. The two-tone

test shown in Figure 18 is per the SMPTE standard for measur-

ing Intermodulation Distortion.

FREQUENCY – kHz

0.001

21012141620

0.0008

0.0006

0.0004

0.0002

–0.0002

–0.0004

–0.0006

–0.0008

–0.001

468 18

Figure 9. Passband Response 8

Mode, 48 kHz Sample

Rate

FREQUENCY – kHz

ATTENUATION – dB

–60

–100

–160

–20

–40

–80

–120

–140

0 150 20050 100 250 300 350

Figure 10. Complete Response, 8

Mode, 48 kHz

Sample Rate

REV. A

AD1853

–11–

Typical Performance Characteristics–

FREQUENCY – kHz

0.5

–10

510152025303540

0.4

0.3

0.2

0.1

–0.1

–0.2

–0.3

–0.4

–0.5

Figure 11. 44 kHz Passband Response 4

Mode, 96 kHz

Sample Rate

FREQUENCY – kHz

2.0

1.5

1.0

–0.5

–1.0

–2.0

10 20 30 40 50 60 70 80

–1.5

0.5

Figure 12. 88 kHz Passband Response 2

Mode, 192 kHz

Sample Rate

FREQUENCY – Hz

dBr

–120

100 1k 10k

–110

–100

–90

–80

–70

–60

–50

Figure 13. THD vs. Frequency Input @ –3 dBFS, SR 48 kHz

150 200

–60

–100

50 100 250

–20

–40

–80

–120

–140

300

FREQUENCY – kHz

–160

Figure 14. Complete Response, 4

Mode, 96 kHz

Sample Rate

FREQUENCY – kHz

–60

–120

–160

–40

–20

–80

–100

–140

0 150 20050 100 250

Figure 15. Complete Response, 2

Mode, 192 kHz

Sample Rate

dBFS

–80

–90

–100

–110

–70

–60

–50

–40

–30

–20

–10

–120 –100 –80 –60 –40 –20 0

Figure 16. THD + N Ratio vs. Amplitude Input 1 kHz,

SR 48 kHz, 24-Bit

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

AD1853JRSZ

Mfr. #:

Buy AD1853JRSZ

Manufacturer:

Analog Devices Inc.

Description:

Audio D/A Converter ICs Stereo 192KHz Mltibt IC

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD1853JRSZ

AD1853JRSZ

Products related to this Datasheet