OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

CAT34C02YI-GT5

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
© Semiconductor Components Industries, LLC, 2012
May, 2018 − Rev. 20
1 Publication Order Number:
CAT34C02/D
CAT34C02
EEPROM Serial 2-Kb I
2
C
forDDR2 DIMM SPD
Description
The CAT34C02 is a EEPROM Serial 2−Kb I
2
C, internally
organized as 16 pages of 16 bytes each, for a total of 256 bytes of 8 bits
each.
It features a 16−byte page write buffer and supports both the
Standard (100 kHz) as well as Fast (400 kHz) I
2
C protocol.
Write operations can be inhibited by taking the WP pin High (this
protects the entire memory) or by setting an internal Write Protect flag
via Software command (this protects the lower half of the memory).
In addition to Permanent Software Write Protection, the
CAT34C02 also features JEDEC compatible Reversible Software
Write Protection for DDR2 Serial Presence Detect (SPD)
applications operating over the 1.7 V to 3.6 V supply voltage range.
The CAT34C02 is fully backwards compatible with earlier
DDR1 SPD applications operating over the 1.7 V to 5.5 V supply
voltage range.
Features
• Supports Standard and Fast I
2
C Protocol
• 1.7 V to 5.5 V Supply Voltage Range
• 16−Byte Page Write Buffer
• Hardware Write Protection for Entire Memory
• Software Write Protection for Lower 128 Bytes
• Schmitt Triggers and Noise Suppression Filters on I
2
C Bus Inputs
(SCL and SDA)
• Low power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial and Extended Temperature Range
• This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant*
Figure 1. Functional Symbol
SDA
SCL
WP
CAT34C02
V
CC
V
SS
A
2
, A
1
, A
0
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
www.onsemi.com
PIN CONFIGURATION
SDA
WP
V
CC
V
SS
A
2
A
1
A
0
1
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
SCL
TSSOP (Y), TDFN (VP2),
UDFN (HU4)
TSSOP−8
Y SUFFIX
CASE 948AL
Device Address InputA
0
, A
1
, A
2
Serial Data Input/OutputSDA
Serial Clock InputSCL
Write Protect InputWP
Power SupplyV
CC
GroundV
SS
FunctionPin Name
PIN FUNCTION
For the location of Pin 1, please consult the
corresponding package drawing.
TDFN−8
VP2 SUFFIX
CASE 511AK
UDFN−8 EP
HU4 SUFFIX
CASE 517AZ
CAT34C02
www.onsemi.com
2
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Rating Unit
Operating Temperature −45 to +130 °C
Storage Temperature −65 to +150 °C
Voltage on Any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V
Voltage on Pin A
0
with Respect to Ground −0.5 to +10.5 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V. During transitions, the voltage on any pin may undershoot to no less than
−1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol Parameter Min Units
N
END
(Note 3) Endurance 1,000,000 Program/ Erase Cycles
T
DR
Data Retention 100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C
Table 3. D.C. OPERATING CHARACTERISTICS
(V
CC
= 1.7 V to 5.5 V, T
A
= −40°C to +85°C and V
CC
= 2.5 V to 5.5 V, T
A
= −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter Test Conditions Min Max Units
I
CC
Supply Current
V
CC
< 3.6 V, f
SCL
= 100 kHz 1
mA
V
CC
> 3.6 V, f
SCL
= 400 kHz 2
I
SB
Standby Current All I/O Pins at GND or V
CC
T
A
= −40°C to +85°C
V
CC
≤ 3.3 V
1 mA
T
A
= −40°C to +85°C
V
CC
> 3.3 V
3
T
A
= −40°C to +125°C 5
I
L
I/O Pin Leakage Pin at GND or V
CC
2
mA
V
IL
Input Low Voltage −0.5 0.3 x V
CC
V
V
IH
Input High Voltage 0.7 x V
CC
V
CC
+ 0.5*
V
OL
Output Low Voltage
V
CC
> 2.5 V, I
OL
= 3 mA 0.4
V
CC
< 2.5 V, I
OL
= 1 mA 0.2
*V
IH
Max = 4 V for SDA and SCL when V
CC
= 0 V.
Table 4. PIN IMPEDANCE CHARACTERISTICS
(V
CC
= 1.7 V to 5.5 V, T
A
= −40°C to +85°C and V
CC
= 2.5 V to 5.5 V, T
A
= −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter Conditions Max Units
C
IN
(Note 4)
SDA I/O Pin Capacitance
V
IN
= 0 V, f = 1.0 MHz, V
CC
= 5.0 V
8
pF
Other Input Pins 6
I
WP
(Note 5) WP Input Current
V
IN
< V
IH
, V
CC
= 5.5 V 130 mA
V
IN
< V
IH
, V
CC
= 3.6 V 120
V
IN
< V
IH
, V
CC
= 1.7 V 80
V
IN
> V
IH
2
I
A
(Note 5) Address Input Current
(A0, A1, A2)
Product Rev H
V
IN
< V
IH
, V
CC
= 5.5 V 50 mA
V
IN
< V
IH
, V
CC
= 3.6 V 35
V
IN
< V
IH
, V
CC
= 1.7 V 25
V
IN
> V
IH
2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull−down reverts to a weak current source.
CAT34C02
www.onsemi.com
3
Table 5. A.C. CHARACTERISTICS
(V
CC
= 1.7 V to 5.5 V, T
A
= −40°C to +85°C and V
CC
= 2.5 V to 5.5 V, T
A
= −40°C to +125°C) (Note 6)
Symbol
Parameter
Standard Fast
Units
Min Max Min Max
F
SCL
Clock Frequency 100 400 kHz
t
HD:STA
START Condition Hold Time 4 0.6
ms
t
LOW
Low Period of SCL Clock 4.7 1.3
ms
t
HIGH
High Period of SCL Clock 4 0.6
ms
t
SU:STA
START Condition Setup Time 4.7 0.6
ms
t
HD:DAT
Data Hold Time 0 0
ms
t
SU:DAT
Data Setup Time 250 100 ns
t
R
(Note 7) SDA and SCL Rise Time 1000 300 ns
t
F
(Note 7) SDA and SCL Fall Time 300 300 ns
t
SU:STO
STOP Condition Setup Time 4 0.6
ms
t
BUF
Bus Free Time Between STOP and START 4.7 1.3
ms
t
AA
SCL Low to SDA Data Out 3.5 0.9
ms
t
DH
Data Out Hold Time 100 100 ns
T
i
(Note 7) Noise Pulse Filtered at SCL and SDA Inputs 100 100 ns
t
SU:WP
WP Setup Time 0 0
ms
t
HD:WP
WP Hold Time 2.5 2.5
ms
t
WR
Write Cycle Time 5 5 ms
t
PU
(Notes 7 & 8) Power−up to Ready Mode 1 1 ms
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
Table 6. THERMAL CHARACTERISTICS (Air velocity = 0 m/s, 4 layers PCB) (Notes 9 and 10)
Part Number Package
q
JA
q
JC
Units
CAT34C02Y TSSOP 64 37 °C/W
CAT34C02VP2 TDFN 92 15 °C/W
CAT34C02HU3 UDFN 101 18 °C/W
CAT34C02HU4 UDFN 101 18 °C/W
9. T
J
= T
A
+ P
D
* q
JA
, where: T
J
is the Junction Temperature, T
A
the Ambient Temperature, P
D
the Power dissipation.
Example: CAT34C02VP2, V
CC
= 3.0 V, I
CCmax
= 1 mA, T
A
= 85°C: T
J
= 85°C + 3 mW * 92°C/W = 85.276°C.
10.T
J
= T
C
+ P
D
* q
JC
, where: T
C
is the Case Temperature, etc.
Table 7. A.C. TEST CONDITIONS
Input Levels 0.2 V
CC
to 0.8 V
CC
Input Rise and Fall Times ≤ 50 ns
Input Reference Levels 0.3 V
CC
, 0.7 V
CC
Output Reference Levels 0.5 V
CC
Output Load Current Source: I
OL
= 3 mA (V
CC
≥ 2.5 V); I
OL
= 1 mA (V
CC
< 2.5 V); C
L
= 100 pF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

CAT34C02YI-GT5

Mfr. #:
Buy CAT34C02YI-GT5
Manufacturer:
ON Semiconductor
Description:
EEPROM 2K-Bit I2C Serial EEPROM,SPD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet