Document #: 001-52849 Rev. *B Page 5 of 7
Application Information
Power Supply Filtering Techniques
As in any high speed analog circuitry, noise at the power supply
pins can degrade performance. To achieve optimum jitter perfor-
mance, use good power supply isolation practices. Figure 8 illus-
trates a typical filtering scheme. Since all the current flows
through pin 1, the resistance and inductance between this pin
and the supply is minimized. A 0.01 or 0.1 µF ceramic chip
capacitor is also located close to this pin to provide a short and
low impedance AC path to ground. A 1 to 10 µF ceramic or
tantalum capacitor is located in the general vicinity of this device
and may be shared with other devices.
Figure 8. Power Supply Filtering
Termination for LVPECL Output
The CY2XP21 implements its LVPECL driver with a current
steering design. For proper operation, it requires a 50 ohm dc
termination on each of the two output signals. For 3.3V
operation, this data sheet specifies output levels for termination
to V
DD
–2.0V. This same termination voltage can also be used for
V
DD
= 2.5V operation, or it can be terminated to V
DD
-1.5V. Note
that it is also possible to terminate with 50 ohms to ground (V
SS
),
but the high and low signal levels differ from the data sheet
values. Termination resistors are best located close to the desti-
nation device. To avoid reflections, trace characteristic
impedance (Z
0
) should match the termination impedance.
Figure 9 shows a standard termination scheme.
Figure 9. LVPECL Output Termination
Crystal Interface
The CY2XP21 is characterized with 18 pF parallel resonant
crystals. The capacitor values shown in Figure 10 are deter-
mined using a 25 MHz 18 pF parallel resonant crystal and are
chosen to minimize the ppm error. Note that the optimal values
for C1 and C2 depend on the parasitic trace capacitance and are
thus layout dependent.
Figure 10. Crystal Input Interface
Board Layout and NC Pin
Pin 5 (NC) does not perform any function on the CY2XP21.
Although not used electrically, it is very useful for heat dissi-
pation. For this reason, users are advised to connect pin 5 to
either a V
DD
or V
SS
plane. This helps to lower the thermal resis-
tance of the board / package combination, thus reducing the die
temperature.
3.3V
10µ
F
0.1μF
V
DD
V
DD
0.01 µF
(Pin 1)
(Pin 8)
CLK
84Ω
84Ω
Z0 = 50Ω
Z0 = 50Ω
3.3V
125Ω 125Ω
IN
CLK#
Device
XIN
XOUT
X1
18 pF Parallel
Crystal
C1
30 pF
C2
27 pF
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