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CY2XP21ZXI

P1-P3P4-P6P7-P7
PRELIMINARY
CY2XP21
125 MHz LVPECL Clock Generator
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-52849 Rev. *B Revised September 22, 2009
Features
■ One LVPECL Output Pair
■ Output Frequency: 112 MHz to 140 MHz
■ External Crystal Frequency: 22.4 MHz to 28 MHz
■ Low RMS Phase Jitter at 125 MHz, using 25 MHz Crystal
(1.875 MHz to 20 MHz): 0.4 ps (Typical)
■ Pb-free 8-Pin TSSOP Package
■ Supply Voltage: 3.3V or 2.5V
■ Commercial and Industrial Temperature Ranges
Functional Description
The CY2XP21 is a PLL (Phase Locked Loop) based high
performance clock generator. It is optimized to generate a
125 MHz clock, which is ideal for 10 Gb Ethernet applications. It
also produces an output frequency that is five times the crystal
frequency. It uses Cypress’s low noise VCO technology to
achieve less than 1 ps typical RMS phase jitter. The CY2XP21
has a crystal oscillator interface input and one LVPECL output
pair.
OUTPUT
DIVIDER
CRYSTAL
OSCILLATOR
CLK#
LOW -N OIS E
PLL
CLK
XOUT
XIN
External
Crystal
Logic Block Diagram
Pinouts
Figure 1. Pin Diagram - 8-Pin TSSOP
1
2
36
7
8
XOUT
XIN NC
VSS
VDD
CLK#
45
VDD
CLK
Table 1. Pin Definition - 8-Pin TSSOP
Pin Number Pin Name I/O Type Description
1, 8 VDD Power 3.3V or 2.5V power supply
2 VSS Power Ground
3, 4 XOUT, XIN XTAL output and input Parallel resonant crystal interface
5 NC No Connect
6,7 CLK#, CLK LVPECL output Differential clock output
[+] Feedback
PRELIMINARY
CY2XP21
Document #: 001-52849 Rev. *B Page 2 of 7
Frequency Table
Inputs
Output Frequency (MHz)
Crystal Frequency (MHz) PLL Multiplier Value
25 5 125
26.6 5 133
Absolute Maximum Conditions
Parameter Description Conditions Min Max Unit
V
DD
Supply Voltage –0.5 4.4 V
V
IN
[1]
Input Voltage, DC Relative to V
SS
–0.5 V
DD
+ 0.5 V
T
S
Temperature, Storage Non operating –65 150 °C
T
J
Temperature, Junction – 135 °C
ESD
HBM
ESD Protection, Human Body Model JEDEC STD 22-A114-B 2000 – V
UL–94 Flammability Rating At 1/8 in. V–0
Θ
JA
[2]
Thermal Resistance, Junction to Ambient 0 m/s airflow 100 °C/W
1 m/s airflow 91
2.5 m/s airflow 87
Notes
1. The voltage on any input or IO pin cannot exceed the power pin during power up.
2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of
copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
Operating Conditions
Parameter Description Min Max Unit
V
DD
3.3V Supply Voltage 3.135 3.465 V
2.5V Supply Voltage 2.375 2.625 V
T
A
Ambient Temperature, Commercial 0 70 °C
Ambient Temperature, Industrial –40 85 °C
T
PU
Power up time for all V
DD
to reach minimum specified voltage (ensure power ramps
is monotonic)
0.05 500 ms
DC Electrical Characteristics
Parameter Description Test Conditions Min Typ Max Unit
I
DD
Operating Supply Current with
output unterminated
V
DD
= 3.465V, Output unterminated – – 125 mA
V
DD
= 2.625V, Output unterminated – – 120 mA
I
DDT
Operating Supply Current with
output terminated
V
DD
= 3.465V, Output terminated – – 150 mA
V
DD
= 2.625V, Output terminated – – 145 mA
V
OH
LVPECL Output High Voltage V
DD
= 3.3V or 2.5V, R
TERM
= 50Ω to
V
DD
– 2.0V
V
DD
–1.15 – V
DD
–0.75 V
V
OL
LVPECL Output Low Voltage V
DD
= 3.3V or 2.5V, R
TERM
= 50Ω to
V
DD
– 2.0V
V
DD
–2.0 – V
DD
–1.625 V
V
OD1
LVPECL Peak-to-Peak Output
Voltage Swing
V
DD
= 3.3V or 2.5V, R
TERM
= 50Ω to
V
DD
– 2.0V
600 – 1000 mV
V
OD2
LVPECL Output Voltage Swing
(V
OH
- V
OL
)
V
DD
= 2.5V, R
TERM
= 50Ω to V
DD
–
1.5V
500 – 1000 mV
[+] Feedback
PRELIMINARY
CY2XP21
Document #: 001-52849 Rev. *B Page 3 of 7
Parameter Measurements
Figure 2. 3.3V Output Load AC Test Circuit
V
OCM
LVPECL Output Common Mode
Voltage (V
OH
+ V
OL
)/2
V
DD
= 2.5V, R
TERM
= 50Ω to V
DD
–
1.5V
1.2 – – V
C
INX
[3]
Pin Capacitance, XIN & XOUT – 4.5 – pF
DC Electrical Characteristics
Parameter Description Test Conditions Min Typ Max Unit
AC Electrical Characteristics
[3]
Parameter Description Conditions Min Typ Max Unit
F
OUT
Output Frequency 112 – 140 MHz
T
R
, T
F
Output Rise or Fall Time 20% to 80% of full output swing – 0.5 1.0 ns
T
Jitter(φ)
RMS Phase Jitter (Random) 125 MHz, (1.875–20 MHz) – 0.4 – ps
T
DC
Output Duty Cycle Measured at zero crossing point 48 – 52 %
T
LOCK
Startup Time Time for CLK to reach valid
frequency measured from the time
V
DD
= V
DD
(min.)
––5ms
Recommended Crystal Specifications
[4]
Parameter Description Min Max Unit
Mode Mode of Oscillation Fundamental
F Frequency 22.4 28 MHz
ESR Equivalent Series Resistance – 50 Ω
C
0
Shunt Capacitance – 7 pF
SCOPE
V
DD
V
SS
LVPECL
50Ω
50Ω
Z = 50Ω
Z = 50Ω
CLK#
CLK
2V
-1.3V +/- 0.165V
[+] Feedback
P1-P3P4-P6P7-P7

CY2XP21ZXI

Mfr. #:
Buy CY2XP21ZXI
Manufacturer:
Cypress Semiconductor
Description:
IC CLOCK GEN PLL LVPECL 8TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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