4
Eye Safety Circuit
For an optical transmitter device to be eye-safe in the
event of a single fault failure, the trans mit ter must either
maintain normal, eye-safe operation or be disabled.
In the HFBR-53A5VEMZ/FMZ there are three key
elements to the laser driver safety circuitry: a monitor
diode, a window detec tor circuit, and direct control of
the laser bias. The window detection circuit monitors
the average optical power using the monitor diode. If
a fault occurs such that the transmitter DC regulation
circuit cannot maintain the preset bias conditions for
the laser emitter within ±20%, the transmitter will
automatically be disabled. Once this has occurred,
only an electrical power reset will allow an attempted
turn-on of the transmitter.
Signal Detect
The Signal Detect circuit provides a deasserted output
signal that implies the link is open or the transmitter
is OFF as dened by the Gigabit Ethernet specication
IEEE 802.3z, Table 38.1. The Signal Detect threshold is
set to transition from a high to low state between the
minimum receiver input optional power and –30 dBm
avg. input optical power indicating a denite optical
fault (e.g., unplugged connector for the receiver or
transmitter, broken ber, or failed far-end transmitter or
data source). A Signal Detect indicating a working link
is functional when receiving encoded 8B/10B
characters. The Signal Detect does not detect receiver
data error or error-rate. Data errors are determined
by Signal processing following the transceiver.
Electromagnetic Interference (EMI)
One of a circuit board designer’s foremost concerns is
the control of electromagnetic emissions from elec-
tronic equipment. Success in controlling gener-
ated Electromagnetic Interference (EMI) enables the
designer to pass a governmental agency’s EMI regulatory
standard; and more importantly, it reduces the
possibility of interference to neighboring equipment.
The EMI performance of an enclosure using these
transceivers is dependent on the chassis design. Avago
encourages using standard RF suppression practices
and avoiding poorly EMI-sealed enclosures.
APPLICATION SUPPORT
Optical Power Budget and Link Penalties
The worst-case Optical Power Budget (OPB) in dB for
a ber-optic link is determined by the dierence be-
tween the minimum transmitter output optical power
(dBm avg) and the lowest receiver sensitivity (dBm
avg). This OPB provides the necessary optical signal
range to establish a working ber-optic link. The OPB is
allocated for the fiber-optic cable length and the
corre sponding link penalties. For proper link
performance, all penalties that affect the link
performance must be accounted for within the link
optical power budget. The Gigabit Ethernet IEEE 802.3z
standard identies, and has modeled, the contributions
of these OPB penalties to establish the link length
requirements for 62.5/125 µm and 50/125 µm
multimode fiber usage. Refer to the IEEE 802.3z
standard and its supplemental documents that develop
the model, empirical results and nal specications.
Data Line Interconnections
Avago’s HFBR-53A5VEMZ/FMZ ber-optic transceiver
is designed for compatible PECL signals. The transmit-
ter inputs are internally ac-coupled to the laser driver
circuit from the transmitter input pins (pins 7, 8). The
transmitter driver circuit for the laser light source is an
ac-coupled circuit. This circuit regulates the output
optical power. The regulated light output will maintain
a constant output optical power provided the data
pattern is reasonably balanced in duty factor. If the
data duty factor has long, con tinu ous state times (low
or high data duty factor), then the output optical power
will gradually change its average output optical power
level to its pre-set value.
The receiver section is internally AC-coupled between
the pre-amplier and the post-amplier stages. The
actual Data and Data-bar outputs of the post-amplier
are ac-coupled to their respective output pins (pins 2, 3).
Signal Detect is a single-ended, TTL output signal that
is dc-coupled to pin 4 of the module. Signal Detect
should not be AC-coupled externally to the follow-on
circuits because of its infrequent state changes.
Caution should be taken to account for the proper
intercon nec tion between the supporting Physical
Layer integrated circuits and this HFBR-53A5VEMZ/
FMZ transceiver. Figure 3 illustrates a recommended
interface circuit for interconnecting to a DC PECL
compatible ber-optic transceiver.
