HEF4894B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 12 July 2012 3 of 18
NXP Semiconductors
HEF4894B-Q100
12-stage shift-and-store register LED driver
5. Pinning information
5.1 Pinning
Fig 3. Logic diagram
001aag119
QP0
QS1
QS2
D Q10SD
CP
STR
OE
QP1 QP10
QP11
STAGE 0 STAGE 11STAGE 1 TO 10
LATCH
DQ
LE
LATCH
DQ
LE
LATCH
DQ
LE
FF0
DQ
CP
FF11
DQ
CP
Fig 4. Pin configuration
HEF4894B-Q100
STR VDD
DOE
CP QP6
QP0 QP7
QP1 QP8
QP2 QP9
QP3 QP10
QP4 QP11
QP5 QS2
VSS QS1
aaa-003548
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
HEF4894B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 12 July 2012 4 of 18
NXP Semiconductors
HEF4894B-Q100
12-stage shift-and-store register LED driver
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; = LOW-to-HIGH clock transition; = HIGH-to-LOW clock transition;
Z = high-impedance OFF-state.
[2] Q10S = the data in register stage 10 before the LOW to HIGH clock transition.
[3] Q11S = the data in register stage 11 before the HIGH to LOW clock transition.
Table 2. Pin description
Symbol Pin Description
D 2 serial input
QP0 to QP11 4, 5, 6, 7, 8, 9, 18, 17, 16, 15, 14, 13 parallel output
QS1 11 serial output
QS2 12 serial output
CP 3 clock input
STR 1 strobe input
OE 19 output enable input
V
DD
20 supply voltage
V
SS
10 ground (0 V)
Table 3. Function table
[1]
At the positive clock edge the information in the 10
th
register stage is transferred to the 11
th
register stage and the QS output
Control Input Parallel output Serial output
CP OE STR D QP0 QPn QS1
[2]
QS2
[3]
L X X Z Z Q10S no change
L X X Z Z no change Q11S
H L X no change no change Q10S no change
HHLZQPn 1 Q10S no change
HHHL QPn1 Q10S no change
H H H no change no change no change Q11S
HEF4894B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 12 July 2012 5 of 18
NXP Semiconductors
HEF4894B-Q100
12-stage shift-and-store register LED driver
7. Limiting values
[1] For SO20 package: P
tot
derates linearly with 8 mW/K above 70 C.
For TSSOP20 package: P
tot
derates linearly with 5.5 mW/K above 60 C.
Fig 5. Timing diagram
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 +18 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
DD
+ 0.5 V - 10 mA
V
I
input voltage 0.5 V
DD
+ 0.5 V
I
OK
output clamping current QSn outputs; V
O
< 0.5 V or V
O
>V
DD
+ 0.5
V
- 10 mA
QPn outputs; V
O
<0.5V - 40 mA
I
I
input leakage current - 10 mA
I
O
output current QSn outputs - 10 mA
QPn outputs - 40 mA
T
stg
storage temperature 65 +150 C
T
amb
ambient temperature 40 +125 C
P
tot
total power dissipation T
amb
= 40 C to +125 C
SO20 and TSSOP20 package
[1]
-500mW
P power dissipation per output - 100 mW

HEF4894BT-Q100,118

Mfr. #:
Manufacturer:
Nexperia
Description:
Counter Shift Registers 12stage shift-and store rgstr LED drvr
Lifecycle:
New from this manufacturer.
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