NLV14013BDR2G

MC14013B
http://onsemi.com
4
SWITCHING CHARACTERISTICS (Note 5) (C
L
= 50 pF, T
A
= 25_C)
Characteristic
Symbol V
DD
Min Typ (Note 6) Max Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
t
TLH
,
t
THL
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q, Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 90 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 42 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 25 ns
t
PLH
t
PHL
5.0
10
15
175
75
50
350
150
100
ns
Set to Q, Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 90 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 42 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 25 ns
5.0
10
15
175
75
50
350
150
100
Reset to Q, Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 265 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 67 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 50 ns
5.0
10
15
225
100
75
450
200
150
Setup Times (Note 7) t
su
5.0
10
15
40
20
15
20
10
7.5
ns
Hold Times (Note 7) t
h
5.0
10
15
40
20
15
20
10
7.5
ns
Clock Pulse Width t
WL
, t
WH
5.0
10
15
250
100
70
125
50
35
ns
Clock Pulse Frequency f
cl
5.0
10
15
4.0
10
14
2.0
5.0
7.0
MHz
Clock Pulse Rise and Fall Time
t
TLH
t
THL
5.0
10
15
15
5.0
4.0
ms
Set and Reset Pulse Width t
WL
, t
WH
5.0
10
15
250
100
70
125
50
35
ns
Removal Times
Set
t
rem
5
10
15
80
45
35
0
5
5
ns
Reset
5
10
15
50
30
25
–35
–10
–5
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
7. Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.
LOGIC DIAGRAM (1/2 of Device Shown)
R
C
D
S
C
C
CC
C
C
C
C
C
C
Q
Q
MC14013B
http://onsemi.com
5
Figure 1. Dynamic Signal Waveforms
(Data, Clock, and Output)
Figure 2. Dynamic Signal Waveforms
(Set, Reset, Clock, and Output)
20 ns 20 ns
D
C
Q
90%
50%
10%
t
su
(H)
t
su
(L)
t
h
t
WH
t
WL
90%
50%
10%
V
DD
V
SS
V
DD
V
SS
V
OH
V
OL
t
TLH
t
THL
t
PHL
t
PLH
90%
50%
10%
Inputs R and S low.
1
f
cl
20 ns 20 ns
SET OR
RESET
CLOCK
Q OR Q
90%
50%
10%
V
DD
V
SS
V
DD
V
SS
V
OH
V
OL
20 ns
20 ns
t
rem
90%
50%
10%
50%
t
PLH
t
PHL
t
w
20 ns
t
w
TYPICAL APPLICATIONS
n−STAGE SHIFT REGISTER
BINARY RIPPLE UP−COUNTER (Divide−by−2
n
)
MODIFIED RING COUNTER (Divide−by−(n+1))
D
CLOCK
n
th
21
QD
C
Q
Q
D
C
Q
Q
D
C
Q
Q
CLOCK
n
th
21
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
Q
T FLIP-FLOP
n
th
21
QD
C
Q
Q
D
C
Q
Q
D
C
Q
Q
CLOCK
MC14013B
http://onsemi.com
6
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
H
14
8
71
M
0.25 B
M
C
h
X 45
SEATING
PLANE
A1
A
M
_
S
A
M
0.25 B
S
C
b
13X
B
A
E
D
e
DETAIL A
L
A3
DETAIL A
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
D 8.55 8.75 0.337 0.344
E 3.80 4.00 0.150 0.157
A 1.35 1.75 0.054 0.068
b 0.35 0.49 0.014 0.019
L 0.40 1.25 0.016 0.049
e 1.27 BSC 0.050 BSC
A3 0.19 0.25 0.008 0.010
A1 0.10 0.25 0.004 0.010
M 0 7 0 7
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
__ __
6.50
14X
0.58
14X
1.18
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

NLV14013BDR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Flip Flops DUAL D-TYPE FLIP-FLOP
Lifecycle:
New from this manufacturer.
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