Philips Semiconductors
P89LPC906/907/908
8-bit microcontrollers with two-clock 80C51 core
Product data Rev. 05 — 17 December 2004 37 of 51
9397 750 14467
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = ‘0’), the UART
is compatible with the conventional 80C51 UART. If enabled, the UART allows writing
to SnBUF while the previous data is being shifted out. Double buffering is only
allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be
disabled (DBMOD = ‘0’).
8.17.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated
when the double buffer is ready to receive new data.
8.17.10 The 9
th
bit (bit 8) in double buffering (Modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as
long as TB8 is updated some time before that bit is shifted out. TB8 must not be
changed until the bit is shifted out, as indicated by the Tx interrupt.
If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8
will be double-buffered together with SBUF data.
8.18 Analog comparator
An analog comparator is provided on the P89LPC906/907/908. Comparator
operation is such that the output is a logical one (which may be read in a register)
when the positive input is greater than the negative input (selectable from a pin or an
internal reference voltage). Otherwise the output is a zero. The comparator may be
configured to cause an interrupt when the output value changes.
The connections to the comparator are shown in Figure 16. The comparator functions
to V
DD
= 2.4 V.
When the comparator is first enabled, the comparator output and interrupt flag are not
guaranteed to be stable for 10 microseconds. The comparator interrupt should not be
enabled during that time, and the comparator interrupt flag must be cleared before
the interrupt is enabled in order to prevent an immediate interrupt service.
When a comparator is disabled the comparator’s output, COx, goes HIGH. If the
comparator output was LOW and then is disabled, the resulting transition of the
comparator output from a LOW to HIGH state will set the comparator flag, CMFx.
This will cause an interrupt if the comparator interrupt is enabled. The user should
therefore disable the comparator interrupt prior to disabling the comparator.
Additionally, the user should clear the comparator flag, CMFx, after disabling the
comparator.
8.19 Internal reference voltage
An internal reference voltage generator may supply a default reference when a single
comparator input pin is used. The value of the internal reference voltage, referred to
as V
REF
, is 1.23 V ±10 %.
8.20 Comparator interrupt
Each comparator has an interrupt flag contained in its configuration register. This flag
is set whenever the comparator output changes state. The flag may be polled by
software or may be used to generate an interrupt.
