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DM74ALS646
Switching Characteristics
over recommended operating free air temperature range
Note 5: These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
Symbol Parameter Conditions
From (Input)
Min Max Units
To (Output)
t
PLH
Propagation Delay Time V
CC
= 4.5V to 5.5V, CBA or CAB
10 30 ns
LOW-to-HIGH Level Output C
L
= 50 pF, to A or B
t
PHL
Propagation Delay Time R
1
= R
2
= 500Ω,CBA or CAB
517ns
HIGH-to-LOW Level Output T
A
= Min to Max to A or B
t
PLH
Propagation Delay Time A or B to
520ns
LOW-to-HIGH Level Output B or A
t
PHL
Propagation Delay Time A or B to
312ns
HIGH-to-LOW Level Output B or A
t
PLH
Propagation Delay Time SBA or SAB
LOW-to-HIGH Level Output to A or B 12 35 ns
(with A or B LOW) (Note 5)
t
PHL
Propagation Delay Time SBA or SAB
HIGH-to-LOW Level Output to A or B 5 20 ns
(with A or B LOW) (Note 5)
t
PLH
Propagation Delay Time SBA or SAB
LOW-to-HIGH Level Output to A or B 6 25 ns
(with A or B HIGH) (Note 5)
t
PHL
Propagation Delay Time SBA or SAB
HIGH-to-LOW Level Output to A or B 5 20 ns
(with A or B HIGH) (Note 5)
t
PZH
Output Enable Time G to
317ns
to HIGH Level Output A or B
t
PZL
Output Enable Time G to
520ns
to LOW Level Output A or B
t
PHZ
Output Disable Time G to
110ns
from HIGH Level Output A or B
t
PLZ
Output Disable Time G to
216ns
from LOW Level Output A or B
t
PZH
Output Enable Time DIR to
630ns
to HIGH Level Output A or B
t
PZL
Output Enable Time DIR to
525ns
to LOW Level Output A or B
t
PHZ
Output Disable Time DIR to
110ns
from HIGH Level Output A or B
t
PLZ
Output Disable Time DIR to
216ns
from LOW Level Output A or B