PCA9548A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
Product data sheet Rev. 5.1 — 1 October 2015 16 of 30
NXP Semiconductors
PCA9548A
8-channel I
2
C-bus switch with reset
12. Dynamic characteristics
[1] Pass gate propagation delay is calculated from the 20 typical R
on
and the 15 pF load capacitance.
[2] After this period, the first clock pulse is generated.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH(min)
of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4] The maximum t
HD;DAT
could be 3.45 s and 0.9 s for Standard-mode and Fast-mode, but must be less than the maximum of t
VD;DAT
or
t
VD;ACK
by a transition time. This maximum must only be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal. If
the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[5] C
b
= total capacitance of one bus line in pF.
[6] Measurements taken with 1 k pull-up resistor and 50 pF load.
Table 9. Dynamic characteristics
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode I
2
C-bus Unit
Min Max Min Max
t
PD
propagation delay from SDA to SDx,
or SCL to SCx
-0.3
[1]
-0.3
[1]
ns
f
SCL
SCL clock frequency 0 100 0 400 kHz
t
BUF
bus free time between a STOP and
START condition
4.7 - 1.3 - s
t
HD;STA
hold time (repeated) START condition
[2]
4.0 - 0.6 - s
t
LOW
LOW period of the SCL clock 4.7 - 1.3 - s
t
HIGH
HIGH period of the SCL clock 4.0 - 0.6 - s
t
SU;STA
set-up time for a repeated START
condition
4.7 - 0.6 - s
t
SU;STO
set-up time for STOP condition 4.0 - 0.6 - s
t
HD;DAT
data hold time 0
[3] [4]
0
[3] [4]
s
t
SU;DAT
data set-up time 250 - 100 - ns
t
r
rise time of both SDA and SCL signals - 1000 20 + 0.1C
b
[5]
300 ns
t
f
fall time of both SDA and SCL signals - 300 20 + 0.1C
b
[5]
300 ns
C
b
capacitive load for each bus line - 400 - 400 pF
t
SP
pulse width of spikes that must be
suppressed by the input filter
-50 - 50ns
t
VD;DAT
data valid time HIGH-to-LOW
[6]
-1 - 1s
LOW-to-HIGH
[6]
-0.6 - 0.6s
t
VD;ACK
data valid acknowledge time - 1 - 1 s
RESET
t
w(rst)L
LOW-level reset time 4 - 4 - ns
t
rst
reset time SDA clear - 500 - 500 ns
t
REC;STA
recovery time to START condition 0 - 0 - ns
