MAX16060/MAX16061/MAX16062
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
16
____________________________________________________________________________________________________________________________________________________________________________
RESET
Output
RESET asserts low when any of the monitored voltages
fall below their respective thresholds or MR is asserted.
RESET remains asserted for the reset timeout period
after all monitored voltages exceed their respective
thresholds and MR is deasserted (see Figure 10). This
open-drain output has a 30µA internal pullup. An external
pullup resistor to any voltage from 0 to 5.5V overrides the
internal pullup if interfacing to different logic supply volt-
ages. Internal circuitry prevents reverse current flow from
the external pullup voltage to V
CC
(Figure 9).
Reset Timeout Capacitor
The reset timeout period can be adjusted to accommo-
date a variety of µP applications. Adjust the reset time-
out period (t
RP
) by connecting a capacitor (C
SRT
)
between SRT and GND. Calculate the reset timeout
capacitor as follows:
Connect SRT to V
CC
for a factory-programmed reset
timeout of 140ms (min).
Manual Reset Input (
MR
)
Many µP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic-low on MR
asserts RESET low. RESET remains asserted while MR
is low, and during the reset timeout period (140ms min)
after MR returns high. The MR input has an internal
20kΩ pullup resistor to V
CC
, so it can be left uncon-
nected if not used. MR can be driven with TTL or
CMOS-logic levels, or with open-drain/collector outputs.
Connect a normally open momentary switch from MR to
GND to create a manual reset function. External
debounce circuitry is not required. If MR is driven from
long cables or if the device is used in a noisy environ-
ment, connecting a 0.1µF capacitor from MR to GND
provides additional noise immunity.
