MAX16060/MAX16061/MAX16062
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
______________________________________________________________________________________________________________________________________________________________________________
7
Pin Description (MAX16060)
PIN NAME FUNCTION
1 IN3 Monitored Input Voltage 3. See Table 1 for the input voltage threshold.
2 IN4 Monitored Input Voltage 4. See Table 1 for the input voltage threshold.
3 WDI
Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period, RESET
is asserted. The timer clears whenever a reset is asserted or a rising or falling edge on WDI is detected.
The watchdog timer enters a startup period that allows 54s for the first transition to occur before a reset.
Leave WDI unconnected to disable the watchdog timer. The WDI unconnected-state detector uses a
small 400nA current. Therefore, do not connect WDI to anything that will source or sink more than
200nA. Note that the leakage current specification for most three-state drivers exceeds 200nA.
4 GND Ground
5V
CC
Unmonitored Power-Supply Input
6 OUT3
O utp ut 3. When the vol tag e at IN 3 fal l s b el ow i ts thr eshol d , OU T3 g oes l ow and stays l ow unti l the vol tag e at
IN 3 exceed s i ts thr eshol d . The op en- d r ai n outp ut has a 30µA i nter nal p ul l up to V
C C
.
7 OUT4
O utp ut 4. When the vol tag e at IN 4 fal l s b el ow i ts thr eshol d , OU T4 g oes l ow and stays l ow unti l the vol tag e at
IN 4 exceed s i ts thr eshol d . The op en- d r ai n outp ut has a 30µA i nter nal p ul l up to V
C C
.
8 MR
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset
timeout period after MR is deasserted. MR is pulled up to V
CC
through a 20kΩ resistor.
9 SRT
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The reset
timeout period can be calculated as follows:
Reset Timeout (s) = 2.06 x 10
6
(Ω) x C
SRT
(F). For the internal timeout period of 140ms (min), connect
SRT to V
CC
.
10 MARGIN
Active-Low Manual Deassert Input. Pull MARGIN low to deassert all outputs (go into high state),
regardless of the voltage at any monitored input.
11 OUT2
O utp ut 2. When the vol tag e at IN 2 fal l s b el ow i ts thr eshol d , OU T2 g oes l ow and stays l ow unti l the vol tag e at
IN 2 exceed s i ts thr eshol d . The op en- d r ai n outp ut has a 30µA i nter nal p ul l up to V
C C
.
12 OUT1
O utp ut 1. When the vol tag e at IN 1 fal l s b el ow i ts thr eshol d , OU T1 g oes l ow and stays l ow unti l the vol tag e at
IN 1 exceed s i ts thr eshol d . The op en- d r ai n outp ut has a 30µA i nter nal p ul l up to V
C C
.
13 RESET
Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its
respective threshold or MR is asserted. RESET remains asserted for the reset timeout period after all
monitored voltages exceed their respective thresholds and MR is deasserted. This open-drain output
has a 30µA internal pullup.
14 IN1 Monitored Input Voltage 1. See Table 1 for the input voltage threshold.
15 IN2 Monitored Input Voltage 2. See Table 1 for the input voltage threshold.
16 TOL
Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL to V
CC
to select 10% threshold tolerance.
—EP
Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low
thermal resistance path from the IC junction to the PCB. Do not use as the electrical connection to GND.
MAX16060/MAX16061/MAX16062
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
8
______________________________________________________________________________________________________________________________________________________________________________
Pin Description (MAX16061)
PIN NAME FUNCTION
1 IN4 Monitored Input Voltage 4. See Table 1 for the input voltage threshold.
2 IN5 Monitored Input Voltage 5. See Table 1 for the input voltage threshold.
3 IN6 Monitored Input Voltage 6. See Table 1 for the input voltage threshold.
4 WDI
Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period, RESET is
asserted and the timer is cleared. The timer also clears whenever a reset is asserted or a rising or falling
edge on WDI is detected. The watchdog timer enters a startup period that allows 54s for the first transition to
occur before a reset. Leave WDI unconnected to disable the watchdog timer.
The WDI unconnected-state detector uses a small 400nA current. Therefore, do not connect WDI to anything
that will source or sink more than 200nA. Note that the leakage current specification for most three-state
drivers exceeds 200nA.
5 GND Ground
6V
CC
Unmonitored Power-Supply Input
7 OUT4
Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low until the voltage at
IN4 exceeds its threshold. The open-drain output has a 30µA internal pullup to V
CC
.
8 OUT5
Output 5. When the voltage at IN5 falls below its threshold, OUT5 goes low and stays low until the voltage at
IN5 exceeds its threshold. The open-drain output has a 30µA internal pullup to V
CC
.
9 OUT6
Output 6. When the voltage at IN6 falls below its threshold, OUT6 goes low and stays low until the voltage at
IN6 exceeds its threshold. The open-drain output has a 30µA internal pullup to V
CC
.
10 MR
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset timeout
period after MR is deasserted. MR is pulled up to V
CC
through a 20kΩ resistor.
11 SRT
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The reset
timeout period can be calculated as follows:
Reset Timeout (s) = 2.06 x 10
6
(Ω) x C
SRT
(F). For the internal timeout period of 140ms (min), connect SRT to
V
CC
.
12 MARGIN
Manual Deassert Input. Pull MARGIN low to deassert all outputs (go into high state), regardless of the voltage
at any monitored input.
13 OUT3
Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low until the voltage at
IN3 exceeds its threshold. The open-drain output has a 30µA internal pullup to V
CC
.
14 OUT2
Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low until the voltage at
IN2 exceeds its threshold. The open-drain output has a 30µA internal pullup to V
CC
.
15 OUT1
Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low until the voltage at
IN1 exceeds its threshold. The open-drain output has a 30µA internal pullup to V
CC
.
16 RESET
Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its respective
threshold or MR is asserted. RESET remains asserted for the reset timeout period after all monitored voltages
exceed their respective thresholds and MR is deasserted. This open-drain output has a 30µA internal pullup.
17 IN1 Monitored Input Voltage 1. See Table 1 for the input voltage threshold.
18 IN2 Monitored Input Voltage 2. See Table 1 for the input voltage threshold.
19 IN3 Monitored Input Voltage 3. See Table 1 for the input voltage threshold.
20 TOL
Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL to V
CC
to
select 10% threshold tolerance.
—EP
Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low thermal
resistance path from the IC junction to the PCB. Do not use as the electrical connection to GND.
MAX16060/MAX16061/MAX16062
1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
______________________________________________________________________________________________________________________________________________________________________________
9
PIN NAME FUNCTION
1 IN5 Monitored Input Voltage 5. See Table 1 for the input voltage threshold.
2 IN6 Monitored Input Voltage 6. See Table 1 for the input voltage threshold.
3 IN7 Monitored Input Voltage 7. See Table 1 for the input voltage threshold.
4 IN8 Monitored Input Voltage 8. See Table 1 for the input voltage threshold.
5 WDI
Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period, RESET is
asserted and the timer is cleared. The timer also clears whenever a reset is asserted or a rising or falling edge on
WDI is detected. The watchdog timer enters a startup period that allows 54s for the first transition to occur before
a reset. Leave WDI unconnected to disable the watchdog timer. The WDI unconnected state detector uses a
small 400nA current. Therefore, do not connect WDI to anything that will source or sink more than 200nA. Note
that the leakage current specification for most three-state drivers exceeds 200nA.
6 GND Ground
7V
CC
Unmonitored Power-Supply Input
8 OUT5
Output 5. When the voltage at IN5 falls below its threshold, OUT5 goes low and stays low until the voltage at IN5
exceeds its threshold. The open-drain output has a 30µA internal pullup to V
CC
.
9 OUT6
Output 6. When the voltage at IN6 falls below its threshold, OUT6 goes low and stays low until the voltage at IN6
exceeds its threshold. The open-drain output has a 30µA internal pullup to V
CC
.
10 OUT7
Output 7. When the voltage at IN7 falls below its threshold, OUT7 goes low and stays low until the voltage at IN7
exceeds its threshold. The open-drain output has a 30µA internal pullup to V
CC
.
11 OUT8
Output 8. When the voltage at IN8 falls below its threshold, OUT8 goes low and stays low until the voltage at IN8
exceeds its threshold. The open-drain output has a 30µA internal pullup to V
CC
.
12 MR
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset timeout period
after MR is deasserted. MR is pulled up to V
CC
through a 20kΩ resistor.
13 SRT
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The reset timeout
period can be calculated as follows:
Reset Ti m eout ( s) = 2.06 x 10
6
( Ω) x C
S RT
( F) . For the i nter nal ti m eout p er i od of 140m s ( m i n) , connect S RT to V
C C
.
14 MARGIN
Margin Disable Input. Pull MARGIN low to deassert all outputs (go into high state), regardless of the voltage at
any monitored input.
15 OUT4
Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low until the voltage at IN4
exceeds its threshold. The open-drain output has a 30µA internal pullup to V
CC
.
16 OUT3
Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low until the voltage at IN3
exceeds its threshold. The open-drain output has a 30µA internal pullup to V
CC
.
17 OUT2
Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low until the voltage at IN2
exceeds its threshold. The open-drain output has a 30µA internal pullup to V
CC
.
18 OUT1
Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low until the voltage at IN1
exceeds its threshold. The open-drain output has a 30µA internal pullup to V
CC
.
19 RESET
Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its respective
threshold or MR is asserted. RESET remains asserted for the reset timeout period after all monitored voltages
exceed their respective thresholds and MR is deasserted. This open-drain output has a 30µA internal pullup.
20 IN1 Monitored Input Voltage 1. See Table 1 for the input voltage threshold.
21 IN2 Monitored Input Voltage 2. See Table 1 for the input voltage threshold.
22 IN3 Monitored Input Voltage 3. See Table 1 for the input voltage threshold.
23 IN4 Monitored Input Voltage 4. See Table 1 for the input voltage threshold.
24 TOL
Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL to V
CC
to select
10% threshold tolerance.
—EP
E xp osed P ad . E P i s i nter nal l y connected to GN D . C onnect E P to the g r ound p l ane to p r ovi d e a l ow ther m al r esi stance
p ath fr om the IC j uncti on to the P C B. D o not use as the el ectr i cal connecti on to GN D .
Pin Description (MAX16062)

MAX16062CTG+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits Quad/Hex/Octal Volt uP Supervisor
Lifecycle:
New from this manufacturer.
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