Document Number: 001-06512 Rev. *H Page 7 of 17
Switching Characteristics
Over the Operating Range
Parameter
[9]
Description
CY62256VN-70
Unit
Min Max
Read Cycle
t
RC
Read cycle time 70 – ns
t
AA
Address to data valid – 70 ns
t
OHA
Data hold from address change 10 – ns
t
ACE
CE LOW to data valid – 70 ns
t
DOE
OE LOW to data valid – 35 ns
t
LZOE
OE LOW to low Z
[10]
5 – ns
t
HZOE
OE HIGH to high Z
[10, 11]
– 25 ns
t
LZCE
CE LOW to low Z
[10]
10 – ns
t
HZCE
CE HIGH to high Z
[10, 11]
– 25 ns
t
PU
CE LOW to power-up 0 – ns
t
PD
CE HIGH to power-down – 70 ns
Write Cycle
[12, 13]
t
WC
Write cycle time 70 – ns
t
SCE
CE LOW to write end 60 – ns
t
AW
Address setup to write end 60 – ns
t
HA
Address hold from write end 0 – ns
t
SA
Address setup to write start 0 – ns
t
PWE
WE pulse width 50 – ns
t
SD
Data setup to write end 30 – ns
t
HD
Data hold from write end 0 – ns
t
HZWE
WE LOW to high Z
[10, 11]
– 25 ns
t
LZWE
WE HIGH to low Z
[10]
10 – ns
Notes
9. Test conditions assume signal transition time of 5 ns or less timing reference levels of V
CC
/2, input pulse levels of 0 to V
CC
, and output loading of the specified I
OL
/I
OH
and 100-pF load capacitance.
10. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
11. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
12. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
13. The minimum write cycle time for Write Cycle No. 3 (WE
Controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
