ADN2813ACPZ-500RL7 Datasheet ADN2813ACPZ-RL7, ADN2813ACPZ-500RL7, ADN2813ACPZ | P19-P21

ADN2813 Data Sheet

Rev. C | Page 18 of 28

SQUELCH MODE

Two SQUELCH modes are available with the ADN2813.

SQUELCH DATAOUT and CLKOUT mode is selected when

CTRLC[1] = 0 (default mode). In this mode, when the

SQUELCH input, Pin 27, is driven to a TTL high state, both

the clock and data outputs are set to the zero state to suppress

downstream processing. If the SQUELCH function is not

required, Pin 27 should be tied to VEE.

SQUELCH DATAOUT or CLKOUT mode is selected when

CTRLC[1] is 1. In this mode, when the SQUELCH input is

driven to a high state, the DATAOUTN/DATA OUTP pins are

squelched. When the SQUELCH input is driven to a low state,

the CLKOUT pins are squelched. This is especially useful in

repeater applications, where the recovered clock may not be

needed.

C INTERFACE

The ADN2813 supports a 2-wire, I

C-compatible serial bus

driving multiple peripherals. Two inputs, serial data (SDA) and

serial clock (SCK), carry information between any devices

connected to the bus. Each slave device is recognized by a

unique address. The ADN2813 has two possible 7-bit slave

addresses for both read and write operations. The MSB of the

7-bit slave address is factory programmed to 1. B5 of the slave

address is set by Pin 19, SADDR5. Slave Address Bits [4:0] are

defaulted to all 0s. The slave address consists of the 7 MSBs of

an 8-bit word. The LSB of the word either sets a read or write

operation (see Figure 7). Logic 1 corresponds to a read

operation, while Logic 0 corresponds to a write operation.

To control the device on the bus, the following protocol must be

followed. First, the master initiates a data transfer by establish-

ing a start condition, defined by a high-to-low transition on

SDA while SCK remains high. This indicates that an address/

data stream follows. All peripherals respond to the start

condition and shift the next eight bits (the 7-bit address and

the R/W bit). The bits are transferred from MSB to LSB. The

peripheral that recognizes the transmitted address responds by

pulling the data line low during the ninth clock pulse. This is

known as an acknowledge bit. All other devices withdraw from

the bus at this point and maintain an idle condition. The idle

condition is where the device monitors the SDA and SCK lines

waiting for the start condition and correct transmitted address.

The R/W bit determines the direction of the data. Logic 0 on

the LSB of the first byte means that the master writes

information to the peripheral. Logic 1 on the LSB of the

first byte means that the master reads information from the

peripheral.

The ADN2813 acts as a standard slave device on the bus.

The data on the SDA pin is eight bits long, supporting the

7-bit addresses, plus the R/W bit. The ADN2813 has eight

subaddresses to enable the user-accessible internal registers

(see Table 6 through Table 10). It, therefore, interprets the first

byte as the device address and the second byte as the starting

subaddress. Auto-increment mode is supported, allowing data

to be read from or written to the starting subaddress and each

subsequent address without manually addressing the subsequent

subaddress. A data transfer is always terminated by a stop

condition. The user can also access any unique subaddress

Stop and start conditions can be detected at any stage of the

data transfer. If these conditions are asserted out of sequence

with normal read and write operations, they cause an immediate

jump to the idle condition. During a given SCK high period, the

user should issue one start condition, one stop condition, or a

single stop condition followed by a single start condition. If an

invalid subaddress is issued by the user, the ADN2813 does not

issue an acknowledge and returns to the idle condition. If the

user exceeds the highest subaddress while reading back in

auto-increment mode, then the highest subaddress register

contents continue to be output until the master device

issues a no acknowledge. This indicates the end of a read. In a

no acknowledge condition, the SDATA line is not pulled low

on the ninth pulse. See Figure 8 and Figure 9 for sample read

and write data transfers and Figure 10 for a more detailed

timing diagram.

REFERENCE CLOCK (OPTIONAL)

A reference clock is not required to perform clock and data

recovery with the ADN2813. However, support for an optional

reference clock is provided. The reference clock can be driven

differentially or single-ended. If the reference clock is not being

used, then REFCLKP should be tied to VCC, and REFCLKN

can be left floating or tied to VEE (the inputs are internally

terminated to VCC/2). See Figure 21 through Figure 23 for

sample configurations.

The REFCLK input buffer accepts any differential signal with a

peak-to-peak differential amplitude of greater than 100 mV (for

example, LVPECL or LVDS) or a standard single-ended, low

voltage TTL input, providing maximum system flexibility.

Phase noise and duty cycle of the reference clock are not

critical, and 100 ppm accuracy is sufficient.

Data Sheet ADN2813

Rev. C | Page 19 of 28

04951-0-021

100k

VCC/2

100k

ADN2813

REFCLKP

REFCLKN

BUFFER

Figure 21. Differential REFCLK Configuration

04951-0-022

100k

VCC/2

100k

ADN2813

REFCLKP

OUT

REFCLKN

BUFFER

VCC

CLK

OSC

Figure 22. Single-Ended REFCLK Configuration

04951-0-023

100k

VCC/2

100k

ADN2813

REFCLKP

REFCLKN

BUFFER

VCC

Figure 23. No REFCLK Configuration

The two uses of the reference clock are mutually exclusive. The

reference clock can be used either as an acquisition aid for the

ADN2813 to lock onto data or to measure the frequency of the

incoming data to within 0.01%. (There is the capability to

measure the data rate to approximately ±10% without the use of

a reference clock.) The modes are mutually exclusive because, in

the first use, the user knows exactly what the data rate is and

wants to force the part to lock onto only that data rate; in the

second use, the user does not know what the data rate is and

wants to measure it.

Lock-to-reference mode is enabled by writing a 1 to I

C Register

Bit CTRLA[0]. Fine data rate readback mode is enabled by

writing a 1 to I

C Register Bit CTRLA[1]. Writing a 1 to both

of these bits at the same time causes an indeterminate state and

is not supported.

Using the Reference Clock to Lock onto Data

In this mode, the ADN2813 locks onto a frequency derived

from the reference clock according to

Data Rate/2

CTRLA[5:2]

= REFCLK/2

CTRLA[7:6]

The user must know exactly what the data rate is and provide a

reference clock that is a function of this rate. The ADN2813 can

still be used as a continuous rate device in this configuration,

provided that the user has the ability to provide a reference clock

that has a variable frequency (see Application Note AN-632).

The reference clock can be anywhere between 10 MHz and

160 MHz. By default, the ADN2813 expects a reference clock of

between 10 MHz and 20 MHz. If it is between 20 MHz and

40 MHz, 40 MHz and 80 MHz, or 80 MHz and 160 MHz, the

user needs to configure the ADN2813 to use the correct

reference frequency range by setting two bits of the CTRLA

Table 11. CTRLA Settings

CTRLA[7:6] Range (MHz) CTRLA[5:2] Ratio

00 10 to 20 0000 1

01 20 to 40 0001 2

10 40 to 80 n 2

11 80 to 160 1000 256

The user can specify a fixed integer multiple of the reference

clock to lock onto using CTRLA[5:2], where CTRLA should be

set to the data rate/DIV_F

REF

, where DIV_F

REF

represents the

divided-down reference referred to the 10 MHz to 20 MHz

band. For example, if the reference clock frequency is

38.88 MHz and the input data rate is 622.08 Mb/s, CTRLA[7:6]

is set to [01] to give a divided-down reference clock of

19.44 MHz. CTRLA[5:2] is set to [0101], that is, 5, because

622.08 Mb/s/19.44 MHz = 2

In this mode, if the ADN2813 loses lock for any reason, it relocks

onto the reference clock and continues to output a stable clock.

While the ADN2813 is operating in lock-to-reference mode, if

the user ever changes the reference frequency, the F

REF

range

(CTRLA[7:6]) or the F

REF

ratio (CTRLA[5:2]), this must be

followed by writing a 0 to 1 transition into the CTRLA[0] bit to

initiate a new lock-to-reference command.

Using the Reference Clock to Measure Data Frequency

The user can also provide a reference clock to measure the

recovered data frequency. In this case, the user provides a

reference clock, and the ADN2813 compares the frequency of

the incoming data to the incoming reference clock and returns a

ratio of the two frequencies to 0.01% (100 ppm). The accuracy

error of the reference clock is added to the accuracy of the

ADN2813 data rate measurement. For example, if a 100 ppm

accuracy reference clock is used, the total accuracy of the

measurement is within 200 ppm.

ADN2813 Data Sheet

Rev. C | Page 20 of 28

The reference clock can range from 10 MHz and 160 MHz.

The ADN2813 expects a reference clock between 10 MHz

and 20 MHz by default. If it is between 20 MHz and 40 MHz,

40 MHz and 80 MHz, or 80 MHz and 160 MHz, the user needs

to configure the ADN2813 to use the correct reference

frequency range by setting two bits of the CTRLA register,

CTRLA[7:6]. Using the reference clock to determine the

frequency of the incoming data does not affect the manner in

which the part locks onto data. In this mode, the reference clock

is used only to determine the frequency of the data. For this

reason, the user does not need to know the data rate to use the

reference clock in this manner.

Prior to reading back the data rate using the reference clock, the

CTRLA[7:6] bits must be set to the appropriate frequency range

with respect to the reference clock being used. A fine data rate

readback is then executed as follows:

1. Write a 1 to CTRLA[1]. This enables the fine data rate

measurement capability of the ADN2813. This bit is level

sensitive and does not need to be reset to perform

subsequent frequency measurements.

2. Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3].

This initiates a new data rate measurement.

3. Read back MISC[2]. If it is 0, the measurement is not

complete. If it is 1, the measurement is complete and the

data rate can be read back on FREQ[22:0]. The time for a

data rate measurement is typically 80 ms.

4. Read back the data rate from FREQ2[6:0], FREQ1[7:0],

and FREQ0[7:0].

The data rate can be determined by

[ ]

(

)

/..

RATESEL

REFCLK

DATARATE

fFREQf

×=

2022

where:

FREQ[22:0] is the reading from FREQ2[6:0] MSByte,

FREQ1[7:0], and FREQ0[7:0] LSByte (see Table 12).

DATAR AT E

is the data rate (Mb/s).

REFCLK

is the REFCLK frequency (MHz).

SEL_ RATE is the setting from CTRLA[7:6].

For example, if the reference clock frequency is 32 MHz,

SEL_RATE = 1, since the CTRLA[7:6] setting is [01], because

the reference frequency falls into the 20 MHz to 40 MHz range.

Assume for this example that the input data rate is 1.25 Gb/s

(GbE). After following Step 1 through Step 4, the value that is

read back on FREQ[22:0] = 0x138800, which is equal to

1.28 × 10

. Plugging this value into the equation yields

128e6 × 32e6/2

(14 + 1)

= 1.25 Gb/s

If subsequent frequency measurements are required, CTRLA[1]

should remain set to 1. It does not need to be reset. The

measurement process is reset by writing a 1 followed by a 0 to

CTRLB[3]. This initiates a new data rate measurement. Follow

Step 2 through Step 4 to read back the new data rate.

Note that a data rate readback is valid only if LOL is low. If LOL

is high, the data rate readback is invalid.

Additional Features Available via the I

C Interface

Coarse Data Rate Readback

The data rate can be read back over the I

C interface to

approximately ±10% without the need of an external reference

clock. A 9-bit register, COARSE_RD[8:0], can be read back

when LOL is deasserted. The eight MSBs of this register are the

contents of the RATE[7:0] register. The LSB of the

COARSE_RD register is Bit MISC[0].

Table 13 provides coarse data rate readback to within ±10%.

LOS Configuration

The LOS detector output, Pin 22, can be configured to be either

active high or active low. If CTRLC[2] is set to Logic 0 (default),

the LOS pin is active high when a loss-of-signal condition is

detected. Writing a 1 to CTRLC[2] configures the LOS pin to be

active low when a loss-of-signal condition is detected.

System Reset

A frequency acquisition can be initiated by writing a 1 followed

by a 0 to the I

C Register Bit CTRLB[5]. This initiates a new

frequency acquisition while keeping the ADN2813 in the

operating mode that it was previously programmed to in

Registers CTRL[A], CTRL[B], and CTRL[C].

Table 12.

D22 D21...D17 D16 D15 D14...D9 D8 D7 D6...D1 D0

FREQ2[6:0] FREQ1[7:0] FREQ0[7:0]

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

ADN2813ACPZ-500RL7

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