REVISION B 4/1/15
840004 DATA SHEET
7 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/
LVTTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
RMS PHASE JITTER
OUTPUT SKEW
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/
LVTTL FREQUENCY SYNTHESIZER
840004 DATA SHEET
8 REVISION B 4/1/15
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 840004 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and
V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each V
DDA
.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
V
DDA
10μF
.01μF
3.3V
.01μF
V
DD
CRYSTAL INPUT INTERFACE
The 840004 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
Figure 2. CRYSTAL INPUt INTERFACE
determined using a 26.5625MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
ICS84332
XTAL_IN
XTAL_OUT
X1
18pF Parallel Cry stal
C2
22p
C1
22p
REVISION B 4/1/15
840004 DATA SHEET
9 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/
LVTTL FREQUENCY SYNTHESIZER
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left fl oating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
REF_CLK I
NPUT:
For applications not requiring the use of the reference clock,
it can be left fl oating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to ground.
LVCMOS C
ONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left fl oating. We recommend that
there is no trace attached.
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface diagram
is shown in Figure 3. The XTAL_OUT pin can be left fl oating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This confi guration requires that the output
Figure 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
impedance of the driver (Ro) plus the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50Ω applications,
R1 and R2 can be 100Ω. This can also be accomplished by
removing R1 and making R2 50Ω.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL _ I N
XTAL _ OU T
.1uf
Rs

840004AGLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 4 LVCMOS OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet