MAX11041
4) The MAX11041 sends the latest keypress type
(K7–K0) stored in the FIFO starting with the most-
significant bit. Afterwards the master must send an
ACK bit.
5) The MAX11041 sends the corresponding keypress
time duration (OF, T6–T0) stored in the FIFO start-
ing with the most significant bit (OF). Afterwards the
master must send an ACK bit.
6) The master must generate a STOP condition.
Slave Address and R/
W
Bit
The MAX11041 includes a 7-bit slave address. The first
5 bits (MSBs) of the slave address are factory-pro-
grammed and always 01000. The logic state of the
address inputs (A1 and A0) determine the last two
LSBs of the device address (see Figure 6). Connect A1
and A0 to V
DD
(logic high) or GND (logic low). A maxi-
mum of four MAX11041 devices can be connected on
the same bus at one time using these address inputs.
The 8th bit of the address byte is a read/write bit (R/W).
If this bit is set to 0, the device expects to receive data.
If this bit is set to 1, the device expects to send data.
Wired Remote Controller
10 ______________________________________________________________________________________
12
3
4
5
6
78
9
0
1
0
0
0A1
A2
SDA
SCL
ACK
S
R/W
Figure 6. Slave Address and R/W Bit
SCL
SDA
S
P
Figure 7. START and STOP Conditions
SCL
SDA
S
1
2
8
9
NOT ACKNOWLEDGE
ACKNOWLEDGE
Figure 8. Acknowledge Bits
MAX11041
Wired Remote Controller
___________________________________________________________________________________ 11
*
Values outside FIFO resistor code are considered invalid.
FIFO RESISTOR CODE*
KEY
STANDARD 1%
RESISTOR VALUE ()
LOWEST HIGHEST
FUNCTION
0 0 0 1 Function 0
1 1470 11 13 Function 1
2 2550 19 21 Function 2
3 3740 27 30 Function 3
4 4990 35 38 Function 4
5 6340 42 46 Function 5
6 7680 50 53 Function 6
7 9310 58 62 Function 7
8 11000 66 70 Function 8
9 13000 74 78 Function 9
10 15000 82 86 Function 10
11 17400 90 94 Function 11
12 20000 98 102 Function 12
13 22600 105 110 Function 13
14 26100 114 119 Function 14
15 30100 123 127 Function 15
16 34000 130 135 Function 16
17 38300 137 142 Function 17
18 44200 146 150 Function 18
19 51100 154 159 Function 19
20 59000 162 166 Function 20
21 68100 170 174 Function 21
22 80600 178 182 Function 22
23 95300 186 190 Function 23
24 118000 194 198 Function 24
25 147000 202 206 Function 25
26 191000 211 214 Function 26
27 261000 218 222 Function 27
28 402000 226 229 Function 28
29 825000 235 237 Function 29
Jack inserted 619000 243 245 Jack inserted
Jack removed 254 255 Jack removed
Table 4. Required Resistor Set for the MAX11041
MAX11041
Bit Transfer
One data bit is transferred during each SCL clock cycle.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is high and stable are considered control signals
(see the
START and STOP Conditions
section). Both
SDA and SCL remain high when the bus is not active.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion, a high-to-low transition on SDA while SCL is high.
The master terminates a transmission with a STOP con-
dition, a low-to-high transition on SDA while SCL is high
(see Figure 7).
Acknowledge Bits
Data transfers are acknowledged with an acknowledge
bit (ACK) or a not-acknowledge bit (NACK). Both the
master and the MAX11041 generates ACK bits. To gen-
erate an ACK, pull SDA low before the rising edge of
the ninth clock pulse and keep it low during the high
period of the ninth clock pulse (see Figure 8). To gener-
ate a NACK, leave SDA high before the rising edge of
the ninth clock pulse and keep it high for the duration of
the ninth clock pulse. Monitoring NACK bits allows for
detection of unsuccessful data transfers. The master
can also use NACK bits to interrupt the current data
transfer to start another data transfer. If the master uses
NACK during a read from the FIFO, the FIFO word
pointer is not incremented and the next FIFO read pro-
duces the same FIFO word. Thus, the master must pro-
vide the ACK bit to advance the FIFO word pointer.
Applications Information
Required Resistor Set
Table 4 shows the required resistor set for 30 key imple-
mentations. Resistors must have a 1% tolerance.
Jack Insertion/Removal Detection
During jack insertion there may be several
false key entries written to the FIFO. When a jack inser-
tion/removal is detected, it is necessary to read the
FIFO repeatedly until the final change in jack state is
located (see Figure 9).
Extended Keypresses
In certain applications, a key triggers different events
depending on the duration of the keypress, simultane-
ous keypresses, or a specific order of keypresses.
Long Keypress Detection
In some applications, the duration of the keypress
determines the event triggered. For example, TALK
dials the entered phone number normally and initiates
voice dialing if it is held down. A second common use
of holding a key down is to generate a continuous
stream of events, such as the volume control or
fast forward.
Wired Remote Controller
12 ______________________________________________________________________________________
Figure 9. Jack Insertion Detection
➀➃
KEY TYPE
JACK
REMOVED
JACK
DETECTED
FALSE
KEYS
TIME
TIME
V
INT
1. JACK INSERTION DETECTED AND ENTERED IN FIFO.
2. JACK REMOVAL DETECTED AND ENTERED IN FIFO.
3. JACK INSERTION DETECTED AND ENTERED IN FIFO.
4. FIFO IS READ UNTIL EMPTY (INT GOES HIGH).
THE LAST READ BEFORE THE EMPTY FIFO IS REACHED
IS THE FINAL STATE OF THE JACK DETECTION.

MAX11041ETC+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Interface - Specialized Wired Remote Controller
Lifecycle:
New from this manufacturer.
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