Data Sheet AD8000
Rev. C | Page 15 of 17
LOW DISTORTION PINOUT
The AD8000 LFCSP features Analog Devices low distortion
pinout. The new pinout lowers the second harmonic distortion
and simplifies the circuit layout. The close proximity of the
non-inverting input and the negative supply pin creates a source
of second harmonic distortion. Physical separation of the non-
inverting input pin and the negative power supply pin reduces
this distortion significantly, as seen in Figure 22.
By providing an additional output pin, the feedback resistor can
be connected directly across Pin 2 and Pin 3. This greatly simplifies
the routing of the feedback resistor and allows a more compact
circuit layout, which reduces its size and helps to minimize
parasitics and increase stability.
The SOIC also features a dedicated feedback pin. The feedback
pin is brought out on Pin 1, which is typically a no connect on
standard SOIC pinouts.
Existing applications that use the standard SOIC pinout can
take full advantage of the performance offered by the AD8000.
For drop-in replacements, ensure that Pin 1 is not connected to
ground or to any other potential because this pin is connected
internally to the output of the amplifier. For existing designs,
Pin 6 can still be used for the feedback resistor.
EXPOSED PADDLE
The AD8000 features an exposed paddle, which can lower the
thermal resistance by 25% compared to a standard SOIC plastic
package. The paddle can be soldered directly to the ground plane
of the board. Figure 53 shows a typical pad geometry for the LFCSP,
the same type of pad geometry can be applied to the SOIC package.
Thermal vias or heat pipes can also be incorporated into the design
of the mounting pad for the exposed paddle. These additional
vias improve the thermal transfer from the package to the PCB.
Using a heavier weight copper on the surface to which the exposed
paddle of the amplifier is soldered also reduces the overall
thermal resistance seen by the AD8000.
05321-034
Figure 53. LFCSP Exposed Paddle Layout
PRINTED CIRCUIT BOARD LAYOUT
Laying out the printed circuit board (PCB) is usually the last
step in the design process and often proves to be one of the
most critical. A brilliant design can be rendered useless because
of a poor or sloppy layout. Because the AD8000 can operate
into the R
F
frequency spectrum, high frequency board layout
considerations must be taken into account. The PCB layout,
signal routing, power supply bypassing, and grounding all must
be addressed to ensure optimal performance.
SIGNAL ROUTING
The AD8000 LFCSP features the new low distortion pinout with a
dedicated feedback pin and allows a compact layout. The dedicated
feedback pin reduces the distance from the output to the inverting
input, which greatly simplifies the routing of the feedback network.
To minimize parasitic inductances, use ground planes under
high frequency signal traces. However, remove the ground
plane from under the input and output pins to minimize the
formation of parasitic capacitors, which degrades phase margin.
Run signals that are susceptible to noise pickup on the internal
layers of the PCB, which can provide maximum shielding.
POWER SUPPLY BYPASSING
Power supply bypassing is a critical aspect of the PCB design
process. For best performance, the AD8000 power supply pins
need to be properly bypassed.
A parallel connection of capacitors from each of the power supply
pins to ground works best. Paralleling different values and sizes
of capacitors helps to ensure that the power supply pins see a
low ac impedance across a wide band of frequencies. This is
important for minimizing the coupling of noise into the amplifier.
Starting directly at the power supply pins, place the smallest
value and sized component on the same side of the board as the
amplifier, and as close as possible to the amplifier, and connected
to the ground plane. Repeat this process for the next larger value
capacitor. It is recommended for the AD8000 that a 0.1 μF ceramic
0508 case be used. The 0508 offers low series inductance and
excellent high frequency performance. The 0.1 μF case provides
low impedance at high frequencies. Place a 10 μF electrolytic
capacitor in parallel with the 0.1 μF. The 10 μF capacitor provides
low ac impedance at low frequencies. Smaller values of electrolytic
capacitors can be used, depending on the circuit requirements.
Additional smaller value capacitors help to provide a low
impedance path for unwanted noise out to higher frequencies
but are not always necessary.
Placement of the capacitor returns (grounds), where the capacitors
enter into the ground plane, is also important. Returning the
capacitors grounds close to the amplifier load is critical for
distortion performance. Keeping the capacitors distance short,
but equal from the load, is optimal for performance.
AD8000 Data Sheet
Rev. C | Page 16 of 17
In some cases, bypassing between the two supplies can help to
improve PSRR and to maintain distortion performance in
crowded or difficult layouts. This is as another option to
improve performance.
Minimizing the trace length and widening the trace from the
capacitors to the amplifier reduce the trace inductance. A series
inductance with the parallel capacitance can form a tank circuit,
which can introduce high frequency ringing at the output. This
additional inductance can also contribute to increased distor-
tion due to high frequency compression at the output. Minimize
the use of vias in the direct path to the amplifier power supply
pins because vias can introduce parasitic inductance, which can
lead to instability. When required, use multiple large diameter
vias because this lowers the equivalent parasitic inductance.
GROUNDING
The use of ground and power planes is encouraged as a method
of proving low impedance returns for power supply and signal
currents. Ground and power planes can also help to reduce
stray trace inductance and to provide a low thermal path for the
amplifier. Do not use ground and power planes under any of the
pins of the AD8000. The mounting pads and the ground or
power planes can form a parasitic capacitance at the amplifiers
input. Stray capacitance on the inverting input and the feedback
resistor form a pole, which degrades the phase margin, leading
to instability. Excessive stray capacitance on the output also
forms a pole, which degrades phase margin.
Data Sheet AD8000
Rev. C | Page 17 of 17
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-012-AA
06-02-2011-B
1.27
0.40
1.75
1.35
2.29
2.29
0.356
0.457
4.00
3.90
3.80
6.20
6.00
5.80
5.00
4.90
4.80
0.10 MAX
0.05 NOM
3.81 REF
0.25
0.17
0.50
0.25
45°
COPLANARITY
0.10
1.04 REF
8
1
4
5
1.27 BSC
S
EATING
PLANE
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
BOTTOM VIEW
TOP VIEW
0.51
0.31
1.65
1.25
Figure 54. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-1)
Dimensions shown in millimeters
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.55
1.45
1.35
1.84
1.74
1.64
0.203 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-229-WEED
12-07-2010-A
P
I
N
1
I
N
D
I
C
A
T
O
R
(
R
0
.
1
5
)
Figure 55. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description Package Option Branding Ordering Quantity
AD8000YRDZ –40°C to +125°C 8-Lead SOIC_N_EP RD-8-1 1
AD8000YRDZ-REEL7 –40°C to +125°C 8-Lead SOIC_N_EP RD-8-1 1,000
AD8000YCPZ-R2 –40°C to +125°C 8-Lead LFCSP CP-8-13 HNB 250
AD8000YCPZ-REEL –40°C to +125°C 8-Lead LFCSP CP-8-13 HNB 5,000
AD8000YCPZ-REEL7 –40°C to +125°C 8-Lead LFCSP CP-8-13 HNB 1,500
1
Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D05321-0-5/16(C)

AD8000YCPZ-REEL

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High Speed Operational Amplifiers 1.5GHz Ultra-Hi Spd w/ Pwr-Down
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