7©2016 Integrated Device Technology, Inc. Revision B, February 18, 2016
85311I Datasheet
Parameter Measurement Information
3.3V Core/ 3.3V LVPECL Output Load AC Test Circuit
Differential Input Level
Part-to-Part Skew
2.5V Core/ 2.5V LVPECL Output Load AC Test Circuit
Output Skew
Propagation Delay
SCOPE
Qx
nQx
V
EE
V
CC
2V
-1.3V ± 0.165V
V
CC
V
EE
nCLK
CLK
tsk(pp)
Part 1
Part 2
nQx
Qx
nQy
Qy
SCOPE
Qx
nQx
V
EE
V
CC
2V
-0.5V ± 0.125V
nQx
Qx
nQy
Qy
t
PD
nCLK
CLK
nQ[0:1]
Q[0:1]
8©2016 Integrated Device Technology, Inc. Revision B, February 18, 2016
85311I Datasheet
Parameter Measurement Information, continued
Output Duty Cycle/Pulse Width/Period Output Rise/Fall Time
Applications Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock swing
is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V and R2/R1 =
0.609.
Figure 1. Single-Ended Signal Driving Differential Input
nQ[0:1]
Q[0:1]
nQ[0:1]
Q[0:1]
V_REF
Single Ended Clock Input
V
CC
CLK
nCLK
R1
1K
C1
0.1u R2
1K
9©2016 Integrated Device Technology, Inc. Revision B, February 18, 2016
85311I Datasheet
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both V
SWING
and V
OH
must meet the V
PP
and V
CMR
input requirements. Figures 2A to 2F show interface
examples for the CLK/nCLK input driven by the most common driver
types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 2A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
Figure 2A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
Figure 2F. CLK/nCLK Input Driven by a
2.5V SSTL Driver
R1
50Ω
R2
50Ω
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
nCLK
3.3V
LVHSTL
IDT
LVHSTL Driver
Differential
Input
H
CSL
*R
3
*
R4
C
L
K
n
C
L
K
3
.
3V
3
.
3V
Diff
e
r
e
nti
a
l
In
p
u
t
CLK
nCLK
Differential
Input
SSTL
2.5V
Zo = 60
Ω
Zo = 60
Ω
2.5V
3.3V
R1
120
Ω
R2
120
Ω
R3
120
Ω
R4
120
Ω

85311AMILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 2 LVPECL OUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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