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85311AMILFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
4©2016 Integrated Device Technology, Inc. Revision B, February 18, 2016
85311I Datasheet
Table 3C. LVPECL DC Characteristics, V
CC
= 3.3V±5%, V
EE
= 0V, T
A
= -40°C to 85°C
NOTE 1: Outputs terminated with 50 to V
CC
– 2V.
Table 3D. LVPECL DC Characteristics, V
CC
= 2.5V±5%, V
EE
= 0V, T
A
= -40°C to 85°C
NOTE 1: Outputs terminated with 50 to V
CC
– 2V.
AC Electrical Characteristics
Table 4A. AC Characteristics, V
CC
= 3.3V±5%, V
EE
= 0V, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
All parameters are measured 500MHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Current; NOTE 1 V
CC
– 1.4 V
CC
– 0.9 V
V
OL
Output Low Current; NOTE 1 V
CC
– 2.0 V
CC
– 1.7 V
V
SWING
Peak-to-Peak Output Voltage Swing 0.65 1.0 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Current; NOTE 1 V
CC
– 1.4 V
CC
– 0.9 V
V
OL
Output Low Current; NOTE 1 V
CC
– 2.0 V
CC
– 1.5 V
V
SWING
Peak-to-Peak Output Voltage Swing 0.4 1.0 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Maximum Output Frequency 1GHz
t
PD
Propagation Delay; NOTE 1 ƒ 1GHz 0.9 2.1 ns
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
156.25MHz, Integration Range
(12kHz – 20MHz)
0.14 ps
tsk(o) Output Skew; NOTE 2, 4 20 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 350 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% @ 50MHz 300 700 ps
odc Output Duty Cycle 45 55 %
5©2016 Integrated Device Technology, Inc. Revision B, February 18, 2016
85311I Datasheet
Table 4B. AC Characteristics, V
CC
= 2.5V±5%, V
EE
= 0V, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
All parameters are measured 500MHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Maximum Output Frequency 1GHz
t
PD
Propagation Delay; NOTE 1 ƒ 1GHz 0.9 2.1 ns
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
156.25MHz, Integration Range
(12kHz – 20MHz)
0.135 ps
tsk(o) Output Skew; NOTE 2, 4 25 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 250 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% @ 50MHz 250 700 ps
odc Output Duty Cycle 45 55 %
6©2016 Integrated Device Technology, Inc. Revision B, February 18, 2016
85311I Datasheet
Additive Phase Jitter (3.3V)
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Offset Frequency (Hz)
SSB Phase Noise dBc/Hz
Additive Phase Jitter @ 156.25MHz
12kHz to 20MHz = 0.14ps (typical)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

85311AMILFT

Mfr. #:
Buy 85311AMILFT
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 2 LVPECL OUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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