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LT1910IS8#PBF

P1-P3P4-P6P7-P9P10-P12P13-P14
LT1910
7
1910fc
For more information www.linear.com/LT1910
OPERATION
also activates the open-collector NPN to pull the FAULT
pin LOW, indicating an overcurrent condition.
When the MOSFET gate voltage is discharged to less than
1.4V, the TIMER pin is released. The 14µA current source
then slowly charges the timing capacitor back to 2.9V
where the charge pump again starts to drive the GATE pin
HIGH. If a fault condition still exists, the sense comparator
threshold will again be exceeded and the timer cycle will
repeat until the fault is removed. The FAULT pin becomes
inactive HIGH if the TIMER pin charges up successfully
above 3.4V (see Figure 1).
3.4V
1910 F01
0V
GATE
TIMER
FAULT
IN
OVERCURRENTNORMAL NORMALOFF
0V
0V
0V
5V
3.5V
2.9V
V
+
12V
Figure 1. Timing Diagram
APPLICATIONS INFORMATION
Input/Supply Sequencing
There are no input/supply sequencing requirements for
the LT1910. The IN pin may be taken up to 15V with the
supply at 0V. When the supply is turned on with the IN
pin set HIGH, the MOSFET turn-on will be inhibited until
the timing capacitor charges up to 2.9V (i.e., for one
restart cycle).
Isolating the Inputs
Operation in harsh environments may require isolation to
prevent ground transients from damaging control logic.
The LT1910 easily interfaces to low cost optoisolators. The
network shown in Figure 2 ensures that the input will be
pulled above 2V, but not exceed the absolute maximum
rating for supply voltages of 12V to 48V over the entire
temperature range. The optoisolator must have less than
20µA of dark current (leakage) at hot in order to maintain
the off state (see Figure 2).
Drain-Sense Configuration
The LT1910 uses supply referenced current sensing. One
input of the current-sense comparator is connected to a
drain-sense pin, while the second input is offset 65mV
below the supply inside the device. For this reason, Pin 8
of the LT1910 must be treated not only as a supply pin,
but also as the reference input for the current-sense
comparator.
Figure 3 shows the proper drain-sense configuration for
the LT1910. Note that the SENSE pin goes to the drain
end of the sense resistor, while the V
+
pin is connected
IN
51k
100k
2k
LOGIC
INPUT
12V TO 48V
LT1910
GND
POWER GROUND
LOGIC GROUND
1
1910 F02
4
FAULT
IN
TIMER
V
+
SENSE
GATE
3
4
2
8
6
5
LT1910
R1
5.1k
24V
5V
FAULT OUTPUT
INPUT
0V
GND
Q1
IRFZ34
24V
2A
SOLENOID
1910 F03
C1
100µF
50V
C
T
1µF
1
R
S
0.02Ω
(PTC)
+
Figure 2. Isolating the Input Figure 3. Drain-Sense Configuration
LT1910
8
1910fc
For more information www.linear.com/LT1910
to the supply at the same point as the positive end of the
sense resistor.
The drain-sense threshold voltage has a positive tempera-
ture coefficient, allowing PTC sense resistors to be used
(see Printed Circuit Board Shunts). The selection of R
S
should be based on the minimum threshold voltage:
R
S
= 50mV/I
SET
Thus the 0.02Ω drain-sense resistor in Figure 3 will yield
a minimum trip current of 2.5A. This simple configuration
is appropriate for resistive or inductive loads that do not
generate large current transients at turn-on.
Automatic Restart Period
The timing capacitor, C
T
, shown in Figure 3 determines
the length of time the power MOSFET is held off follow-
ing a current limit trip. Curves are given in the Typical
Performance Characteristics to show the restart period
for various values of C
T
. For example, C
T
= 0.33µF yields
a 50ms restart period.
Defeating Automatic Restart
Some applications are required to remain off after a fault
occurs. When the LT1910 is being driven from CMOS logic,
this can be easily implemented by connecting resistor R2
between the IN and TIMER pins as shown in Figure 4. R2
supplies the sustaining current for an internal SCR which
latches the TIMER pin LOW under a fault condition. The
FAULT pin is set active LOW when the TIMER pin falls below
3.3V. This keeps the MOSFET gate from turning on and the
APPLICATIONS INFORMATION
FAULT pin from resetting HIGH until the IN pin has been
recycled. C
T
is used to prevent the FAULT pin from glitch-
ing whenever the IN pin recycles to turn on the MOSFET
unsuccessfully under an existing fault condition.
Inductive vs Capacitive Loads
Turning on an inductive load produces a relatively benign
ramp in MOSFET current. However, when an inductive
load is turned off, the current stored in the inductor needs
somewhere to decay. A clamp diode connected directly
across each inductive load normally serves this purpose.
If a diode is not employed, the LT1910 clamps the MOSFET
gate 0.7V below ground. This causes the MOSFET to resume
conduction during the current decay with (V
+
+ V
GS
+ 0.7V)
across it, resulting in high dissipation peaks.
Capacitive loads exhibit the opposite behavior. Any load
that includes a decoupling capacitor will generate a current
equal to C
LOAD
• (∂V/∂t) during capacitor in-rush. With
large electrolytic capacitors, the resulting current spike
can play havoc with the power supply and false trip the
current-sense comparator.
Turn-on ∂V/∂t is controlled by the addition of the simple
network shown in Figure 5. This network takes advantage of
the fact that the MOSFET acts as a source follower during
turn-on. Thus the ∂V/∂t on the source can be controlled
by controlling the ∂V/∂t on the gate.
IN
TIMER
FAULT
5V
FAULT OUTPUT
R1
5.1k
ON = 5V
OFF = 0V
LT1910
GND
1
1910 F04
4
R2
2k
C
T
1µF
2
3
5V
CMOS
LOGIC
V
+
SENSE
8
6
LT1910
1
GND
Q1
IRFZ34
15V
1N4744
C
LOAD
C2
50µF
50V
1910 F05
R
S
0.01Ω
+
+
C
D
R
D
(≤10k)
1N4148
24V
CURRENT LIMIT
DELAY NETWORK
C1
1N4148
R1
100k
R2
100k
∂V/∂t CONTROL NETWORK
GATE
5
Figure 4. Latch-Off Configuration (Autorestart Defeated) Figure 5. Control and Current Limit Delay
LT1910
9
1910fc
For more information www.linear.com/LT1910
APPLICATIONS INFORMATION
The turn-on current spike into C
LOAD
is estimated by:
IC•
V–V
R1•C1
PEAK
LOAD
G
TH
=
where V
TH
is the MOSFET gate threshold voltage. V
G
is
obtained by plotting the equation:
I
V
R1
GATE
GATE
=
on the graph of Gate Drive Current (I
GATE
) vs Gate Voltage
(V
GATE
) as shown in Figure 6. The value of V
GATE
at the
intersection of the curves for a given supply is V
G
. For
example, if V
+
= 24V and R1 = 100k, then V
G
= 18.3V. For
V
TH
= 2V, C1 = 0.1µF and C
LOAD
= 1000µF, the estimated
I
PEAK
= 1.6A. The diode and the second resistor in the
network ensure fast current limit turn-off.
When turning off a capacitive load, the source of the
MOSFET can “hang up” if the load resistance does not
discharge C
LOAD
as fast as the gate is being pulled down.
If this is the case, a 15V Zener may be added from gate to
source to prevent V
GS(MAX)
from being exceeded.
R
D
and C
D
delay the overcurrent trip for drain currents up
to approximately 10 • I
SET
, above which the diode conducts
and provides immediate turn-off (see Figure 7). To ensure
proper operation of the timer, C
D
must be ≤C
T
.
GATE VOLTAGE (V)
0
GATE DRIVE CURRENT (µA)
300
400
500
30
50
1910 F06
200
100
0
10 20 40
600
700
800
60
V
+
= 48V
I
GATE
=
V
GATE
/10
5
V
+
= 24V
V
+
= 12V
V
+
= 8V
Figure 6. Gate Drive Current vs Gate Voltage
Adding Current Limit Delay
When capacitive loads are being switched or in very noisy
environments, it is desirable to add delay in the drain
current-sense path to prevent false tripping (inductive
loads normally do not need delay). This is accomplished
by the current limit delay network shown in Figure 5.
MOSFET DRAIN CURRENT (1 = SET CURRENT)
1
0.01
TRIP DELAY TIME (1 = R
D
C
D
)
0.1
1
10
10 100
1910 F07
Figure 7. Current Limit Delay Time
Printed Circuit Board Shunts
The sheet resistance of 1oz copper clad is approximately
5 • 10
–4
Ω/square with a temperature coefficient of
0.39%/°C. Since the LT1910 drain-sense threshold has a
similar temperature coefficient (0.33%/°C), this offers the
possibility of nearly zero TC current sensing using the “free”
drain-sense resistor made out of PC trace material.
A conservative approach is to use 0.02" of width for each
1A of current for 1oz copper. Combining the LT1910 drain
sense threshold with the 1oz copper resistance results in
a simple expression for width and length:
Width (1oz Cu) = 0.02" • I
SET
Length (1oz Cu) = 2"
The width for 2oz copper would be halved while the length
would remain the same.
Bends may be incorporated into the resistor to reduce
space; each bend is equivalent to approximately 0.6 •the
width of a straight length. Kelvin connection should be
employed by running a separate trace from the ends of
the resistor back to the LT1910’s V
+
and SENSE pins. See
Application Note 53 for further information on printed
circuit board shunts.
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LT1910IS8#PBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Gate Drivers Protected Hi Side MOSFET Drvr
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