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MAX4575EUA+

P1-P3P4-P6P7-P9P10-P12
Detailed Description
The MAX4575/MAX4576/MAX4577 are dual SPST
CMOS analog switches with circuitry providing ±15kV
ESD protection on the NO and NC pins. The CMOS
switch construction provides rail-to-rail signal handling
while consuming virtually no power. Each of the two
switches is independently controlled by a TTL/CMOS-
level-compatible digital input.
Applications Information
Do not exceed the absolute maximum ratings because
stresses beyond the listed ratings may cause perma-
nent damage to the device.
Proper power-supply sequencing is recommended for
all CMOS devices. Always sequence V+ on first, fol-
lowed by the logic inputs, NO/NC, or COM.
Operating Considerations for
High-Voltage Supply
The MAX4575/MAX4576/MAX4577 are capable of
+12V single-supply operation with some precautions.
The absolute maximum rating for V+ is +13V (refer-
enced to GND). When operating near this region,
bypass V+ with a minimum 0.1µF capacitor to ground
as close to the IC as possible.
±15kV ESD Protection
The MAX4575/MAX4576/MAX4577 are ±15kV ESD pro-
tected (according to IEC 1000-4-2) at the NC/NO termi-
nals. To accomplish this, bidirectional SCRs are
included on-chip between these terminals. When the
voltages at these terminals go Beyond-the-Rail™, the
corresponding SCRs turns on in a few nanoseconds
MAX4575/MAX4576/MAX4577
±15kV ESD-Protected, Low-Voltage, Dual, SPST,
CMOS Analog Switches
_______________________________________________________________________________________ 7
t
R
< 20ns
t
F
< 20ns
50%
0
LOGIC
INPUT
R
L
300Ω
NO_/NC_
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
COM (
R
L
)
R
L
+ R
ON
SWITCH
INPUT
IN
t
OFF
0
COM
SWITCH
OUTPUT
0.9 x V
0UT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
V+
C
L
35pF
V+
V
OUT
V
COM
MAX4575
MAX4576
MAX4577
V+
Figure 1. Switching Time
Figure 2. Off-Isolation/On-Channel Bandwidth
IN
V
IL
OR
V
IH
SIGNAL
GENERATOR 0dBm
V+
10nF
ANALYZER
NO_/NC_
R
L
GND
COM
V+
MAX4575
MAX4576
MAX4577
Beyond-the-Rail is a trademark of Maxim Integrated Products.
MAX4575/MAX4576/MAX4577
±15kV ESD-Protected, Low-Voltage, Dual, SPST,
CMOS Analog Switches
8 _______________________________________________________________________________________
and bypass the surge safely to ground. This method is
superior to using diode clamps to the supplies
because, unless the supplies are very carefully decou-
pled through low-ESR capacitors, the ESD current
through the diode clamp could cause a significant
spike in the supplies. This may damage or compromise
the reliability of any other chip powered by those same
supplies.
There are diodes from NC/NO to the supplies in addi-
tion to the SCRs. There is a resistance in series with
each of these diodes to limit the current into the sup-
plies during an ESD strike. The diodes protect these
terminals from overvoltages that are not a result of ESD
strikes. These diodes also protect the device from
improper power-supply sequencing.
Once the SCR turns on because of an ESD strike, it
continues to be on until the current through it falls
below its “holding current.” The holding current is typi-
cally 110mA in the positive direction (current flowing
into the NC/NO terminal) at room temperature (see SCR
Holding Current vs. Temperature in the Typical
Operating Characteristics). Design the system so that
any sources connected to NC/NO are current limited to
a value below the holding current to ensure the SCR
Figure 5. Crosstalk
SIGNAL
GENERATOR 0dBm
V+
10nF
ANALYZER
NO2/NC2
R
L
GND
COM1
0 OR 2.4V
IN1
NO1/NC1
50Ω
COM2
IN2
0 OR
2.4V
NC
V+
MAX4575
MAX4576
MAX4577
Figure 4. Channel Off/On-Capacitance
CAPACITANCE
METER
NO_/NC_
COM
GND
IN
10nF
V+
f = 1MHz
V+
MAX4575
MAX4576
MAX4577
V
IL
OR
V
IH
V
GEN
GND
NO_/NC_
C
L
V
OUT
V+
V
OUT
∆V
OUT
Q = (∆V
OUT
)(C
L
)
COM
OFF
ON
OFF
IN
V
IN
V+
R
GEN
IN
MAX4575
MAX4576
MAX4577
Figure 3. Charge Injection
MAX4575/MAX4576/MAX4577
±15kV ESD-Protected, Low-Voltage, Dual, SPST,
CMOS Analog Switches
turns off when the ESD event is finished and normal
operation may be resumed. Also, keep in mind that the
holding current varies significantly with temperature.
The worst case is at +85°C when the holding currents
drop to 70mA. Since this is a typical number to guaran-
tee turn-off of the SCRs under all conditions, the sources
connected to these terminals should be current limited
to not more than half this value. When the SCR is
latched, the voltage across it is about 3V, depending on
the polarity of the pin current. The supply voltages do
not affect the holding current appreciably. The sources
connected to the COM side of the switches do not need
to be current limited since the switches turn off internally
when the corresponding SCR(s) latches.
Even though most of the ESD current flows to GND
through the SCRs, a small portion of it goes into V+.
Therefore, it is a good idea to bypass the V+ with 0.1µF
capacitors directly to the ground plane.
ESD protection can be tested in various ways. Trans-
mitter outputs and receiver inputs are characterized for
protection to the following:
• ±15kV using the Human Body Model
• ±8kV using the Contact Discharge method speci-
fied in IEC 1000-4-2 (formerly IEC 801-2)
• ±15kV using the Air-Gap Discharge method speci-
fied in IEC 1000-4-2 (formerly IEC 801-2).
ESD Test Conditions
Contact Maxim Integrated Products for a reliability
report that documents test setup, methodology, and
results.
Human Body Model
Figure 6 shows the Human Body Model and Figure 7
shows the waveform it generates when discharged into
a low impedance. This model consists of a 100pF
capacitor charged to the ESD voltage of interest, which
can be discharged into the test device through a 1.5kΩ
resistor.
IEC 1000-4-2
The IEC 1000-4-2 standard covers ESD testing and per-
formance of finished equipment; it does not specifically
refer to integrated circuits. The MAX4575/MAX4576/
MAX4577 enable the design of equipment that meets
Level 4 (the highest level) of IEC 1000-4-2, without addi-
tional ESD protection components.
The major difference between tests done using the
Human Body Model and IEC 1000-4-2 is higher peak
current in IEC 1000-4-2. Because series resistance is
lower in the IEC 1000-4-2 ESD test model (Figure 8),
the ESD withstand voltage measured to this standard is
generally lower than that measured using the Human
Body Model. Figure 9 shows the current waveform for
the ±8kV IEC 1000-4-2 Level 4 ESD Contact Discharge
test.
The Air-Gap test involves approaching the device with
a charged probe. The Contact Discharge method con-
nects the probe to the device before the probe is ener-
gized.
Chip Information
TRANSISTOR COUNT: 78
PROCESS: CMOS
_______________________________________________________________________________________ 9
P1-P3P4-P6P7-P9P10-P12

MAX4575EUA+

Mfr. #:
Buy MAX4575EUA+
Manufacturer:
Maxim Integrated
Description:
Analog Switch ICs Dual SPST CMOS Analog Switch
Lifecycle:
New from this manufacturer.
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