MAX707, MAX708
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7
RESET Signal Integrity During Power−Down
The MAX707/708 RESET output is valid until V
CC
falls
below 1.0 V. Then, the output becomes an open circuit and
no longer sinks current. This means CMOS logic inputs of
the mP will be floating at an undetermined voltage. Most
digital systems are completely shutdown well above this
voltage. However, in the case RESET must be maintained
valid to V
CC
= 0 V, a pull down resistor must be connected
from RESET to ground to discharge stray capacitances and
hold the output low (Figure 14). This resistor value, though
not critical, should be chosen large enough not to load
RESET and small enough to pull it to ground. R = 100 kW
will be suitable for most applications.
RESET
Figure 14. Ensuring RESET Valid to V
CC
= 0 V
V
CC
GND
MAX707/708
R
100 k
Interfacing with mPs with Bidirectional I/O Pins
Some mPs have bidirectional reset pins. If, for example,
the RESET output is driven high and the mP wants to put it
low, indeterminate logic level may result. This can be
avoided by adding a 4.7 kW resistor in series with the output
of the MAX707/708 (Figure 15). If there are other
components in the system that require a reset signal, they
should be buffered so as not to load the reset line. If the other
components are required to follow the reset I/O of the mP, the
buffer should be connected as shown with the solid line.
RESETRESET
Figure 15. Interfacing to Bidirectional Reset I/O
GND
MAX707/708
V
CC
GND
V
CC
BUFFER
m P
RESET TO
OTHER SYSTEM
COMPONENTS
4.7 k
Monitoring Additional Supply Levels
When connecting a voltage divider to PFI and adjusting it
properly, you can monitor a voltage different than the
unregulated DC one. As shown in Figure 16, to increase
noise immunity, hysteresis may be added to the power−fail
comparator just by a resistor between PFO and PFI. Not to
unbalance the potential divider network, R3 should be 10
times the sum of the two resistors R1 and R2. If required, a
capacitor between PFI and GND will reduce the sensitivity
of the circuit to high−frequency noise on the line being
monitored. The PFO output may be connected to MR input
to generate a low level on the RESET when V
CC
_1
drops out
of tolerance. Thus a RESET is generated when one of the
two voltages is below its threshold level.
MAX707/708
Figure 16. Monitoring Additional Supply Levels
GND
V
CC
GND
V
CC
m P
RESET
MR
PFO
PFI
RESET
R1
R2
R3
V
CC_1
V
CC_2
V
CC_3
PFO
V
CC_1
V
CC_2
0 V
0 V V
L
V
H
V
L
+ 1.25 ) R1
ǒ
1.25
R2
)
1.25 * V
cc_2
R3
Ǔ
V
H
+ 1.25 (1 ) R1
ǒ
R2 ) R3
R2 R3
Ǔ
)
V
HYS
+ V
H
* V
L
+
R1 V
cc_2
R3
