LTC6601-1
13
66011f
V
+
, V
–
(Pins 14, 13): Power Supply Pins. It is critical that
close attention be paid to supply bypassing. For single
supply applications (Pin 13 grounded), it is recommended
that a high quality 0.1F surface mount ceramic bypass
capacitor (X7R dielectric for instance) be placed between
Pins 14 and 13, with direct short connections. Pin 13
should be tied directly to a low impedance ground plane
with minimal routing. For dual (split) power supplies, it
is recommended that at least two additional high quality
0.1F ceramic capacitors are used to bypass V
+
to ground
and V
–
to ground, again with minimal routing. For driving
large loads (< 200Ω), additional bypass capacitance may
be added for optimal performance. Keep in mind that small
geometry (e.g., 0603) surface mount ceramic capacitors
have a much lower ESL than do leaded capacitors, and
perform best in high speed applications.
C7, C8 (Pins 17, 16): Input to a trimmed 10.55pF, 21.1pF
capacitor which feeds the amplifi er noninverting sum-
ming node. Typically, either fl oat or tie to OUT
–
. For best
performance, stray capacitance should be kept as low as
possible by keeping printed circuit connections as short
and direct as possible.If necessary, strip back the sur-
rounding ground plane away from these pins.
C5, C6 (Pins 19, 18): Input to a trimmed 16.1pF, 33.3pF
capacitor which feeds an inverting summing node. Typi-
cally, either fl oat or tie to OUT
+
. If either of these pins are
tied to a low impedance source other than OUT
+
, a re-
sistance of at least 25Ω should be placed in series. For
best performance, it is highly recommended that stray
capacitance be kept to as low as possible by keeping printed
circuit connections as short and direct as possible, and if
necessary, stripping back nearby surrounding reference
plane away from these pins.
Exposed Pad (Pin 21): Always tie the underlying Exposed
Pad to V
–
(Pin 13). If split supplies are used, do not tie
the pad to ground. Tie it to V
–
.
PIN FUNCTIONS
(Refer to the Block Diagram)
