5P35023-000NLGI Datasheet 5P35023-000NLGI, 5P35023-000NLGI8 | P7-P9

JANUARY 25, 2017 7 VERSACLOCK

Programmable Clock Generator

5P35023 DATASHEET

Timer Function Description

1. The timer function can be used together with the DFC -Dynamic Frequency Control function or with another PLL frequency

programming.

2. The timer provides 4 different delay times as 0.5 sec - 1 sec - 2 sec - 4 sec by two bits selection.

3. The timeout flag will be set when timer times out, and the flag can be cleared by writing 0 to timer enable bit.

4. When timer times out, RESET pin can generate a 250ms pulse signal if RESET control bit is enabled.

5. When timer times out, DFC stage will switch back to DFC00 setting if DFC function is enabled and DFC function will be

disabled after RESET.

OE Pin Function

OE pins in the 5P35023 have multiple functions. The OE pins can be configured as output enable control (OE) or chip power

down control (PD#) or Proactive Power Saving function (PPS). Furthermore, the OE pins can be configured as single or two pin

dynamic Frequency control (DFC), or the RESET out function that is associated with the Timer function.

OE Pin Function Table

Select delay time 0.5 ~ 4.0 seconds and enable Timer

Program New VCO frequency or enable DFC

System functional check

Disable Timer

Timerout Flag set and generate RESET pluse

Timer continue if system is not able to stop timer

OE1 OE2 OE3

SE output enable/disable

SE1 (Default) SE2 (Default) SE3(Default)

DIFF output enable/disable

- DIFF1/DIFF2 -

Global Power Down (PD#)

PD# - -

Proactive Power Saving input

SE1_PPS SE2_PPS SE3_PPS

DOC control (Only PLL2)

DFC0 - DFC1

RESET OUT

- RESET OUT -

Function

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PROGRAMMABLE CLOCK GENERATOR 8 JANUARY 25, 2017

5P35023 DATASHEET

OE Pin Function Summary

PD# Priority Table

Reference Input and Selection

By programming, the 5P35023 accepts 8MHz ~40MHz crystal input, 8MHz to 125MHz differential clocks input or 1MHz

~125MHz LVCMOS (to X1) input. See below reference circuit for details.

Crystal Input (X1/X2)

The crystal oscillators should be fundamental mode quartz crystals; overtone crystals are not suitable. Crystal frequency should

be specified for parallel resonance with 40MHz maximum.

A crystal manufacturer will calibrate its crystals to the nominal frequency with a certain load capacitance value. When the

oscillator load capacitance matches the crystal load capacitance, the oscillation frequency will be accurate as 0 PPM. When the

oscillator load capacitance is lower than the crystal load capacitance, the oscillation frequency will be higher than nominal. In

order to get an accurate oscillation frequency, the matching the oscillator load capacitance with the crystal load capacitance is

required.

To set the oscillator load capacitance, 5P35023 has built-in two programmable tuning capacitors inside the chip, one at XIN and

one at XOUT. They can be adjusted independently. The value of each capacitor is composed of a fixed capacitance amount plus

a variable capacitance amount set with the XTAL[7:0] register. Adjustment of the crystal tuning capacitors allows for maximum

flexibility to accommodate crystals from various manufacturers. The range of tuning capacitor values available are in accordance

with the following table.

OE1: SE1

OE2: SE2

OE2: SE3

OE2: DIFF1/DIFF2

OE1: PD#

OE1: SE1_PPS

OE2: SE2_PPS

OE3: SE3_PPS

OE1:DFC0

OE3/DFC1

Config OE3 as SE3_PPS (Proactive Power Saving) function pin

Config OE1 as DFC0 control pin0

Config OE3 as DFC1 control pin1

OE3 only control SE3 enable/disable, other outputs are not affected by this pin status

OE2 control Differential outputs 1 and 2 only, other SE outputs are not affected by this pin status

OE1 control chip global power down (PD#) except 32.768KHz on OE1 (when 32K is enabled),

Whenthe PD# pin is active low, the chip goes to lowest power down mode and all outputs are disabled

except 32Khz output and only keep 32K/Xtal calibriation.

Config OE1 as SE1_PPS (Proactive Power Saving) funciton pin

Config OE2 as SE2_PPS (Proactive Power Saving) function pin

OE1 only control SE1 enable/disable, other outputs are not affected by this pin status

OE2 only control SE2 enable/disable, other outputs are not affected by this pin status

PD# I2C_OE_EN_bit

SE1/2/3, DIFF1/DIFF2

SEx_PPS

output Notes

0 x x stop 32KHz free run

10xstop

110stop

1 1 1 running

JANUARY 25, 2017 9 VERSACLOCK

Programmable Clock Generator

5P35023 DATASHEET

Programmable Tuning Caps Table

XTAL[4:0] = (XTAL CL - 7pF ) *2 (Eq.1)

Equation 1 and the table of XTAL[7:0] tuning capacitor characteristics show that the parallel tuning capacitance can be set

between 4.5pF to 12.5pF with a resolution of 0.25 pF.

For a crystal CL= 8pF, where CL is the parallel capacity specified by the crystal vendor that sets the crystal frequency to the

nominal value. Under the assumptions that the stray capacity between the crystal leads on the circuit board is zero and that no

external tuning caps are placed on the crystal leads, then the internal parallel tuning capacity is equal to the load capacity

presented to the crystal by the device.

The internal load capacitors are true parallel-plate capacitors for ultra-linear performance. Parallel-plate capacitors were chosen

to reduce the frequency shift that occurs when non-linear load capacitance interacts with load, bias, supply, and temperature

changes. External non-linear crystal load capacitors should not be used for applications that are sensitive to absolute frequency

requirements.

Spread Spectrum

The 5P35023 supports spread spectrum clocks from PLL1 and PLL2; the PLL1 built-in with Analog spread spectrum and PLL2

has Digital spread spectrum.

Analog Spread Spectrum

Please refer to programming guide.

Parameter Bits Range Min (pF) Max (pF)

Xtal [7:0] 4*2 +1/+2/+4/+8 pF 0 15pF

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P34

5P35023-000NLGI

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5P35023-000NLGI

5P35023-000NLGI

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