MAX1005EEE+T Datasheet MAX1005CEE+, MAX1005CEE+T, MAX1005EEE+T | P4-P6

CONDITIONS

MAX1005

IF Undersampler

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VCCA = VCCD = 3.0V, f

CLK

= 15MHz, R

= ∞, T

= T

MIN

to T

MAX

, unless otherwise noted.)

RXEN, TXEN;

VCCD = 2.7V

to 3.6V

D0–D6, CLK; VCCD = 2.7V to 5.5V

≤ 12.5pF

= +25°C (Note 6)

RXEN, TXEN;

VCCD = 3.6V

to 5.5V

D0–D6, CLK; TXEN = 1, RXEN = 0 (Note 6)

CONDITIONS

±2

±1

µA

-1 7

Input Current

ns13 20t

ADC CLK to Output Data Valid

%45 55CLK Duty Cycle

ns5 0.3t

HOLD

DAC Data Hold Time

ns5 0.6t

DAC Data Setup Time

±1

±4

pF8C

Input Capacitance

UNITSMIN TYP MAXSYMBOLPARAMETER

TXEN = 0 and RXEN = 1, or

TXEN = 1 and RXEN = 0

TXEN = RXEN

TXEN = 0 and RXEN = 1, or

TXEN = 1 and RXEN = 0

Note 1: TXEN = 1, RXEN = 0. All DAC transfer function parameters are measured differentially from AIO+ to AIO- using the End-

Point Linearity method.

Note 2: f

= 4.3MHz digital sine wave applied to DAC data inputs; f

CLK

= 15MHz. The reference frequency (f

REF

) is defined to be

10.7MHz (f

CLK

- f

). All frequency components present in the DAC output waveform except for f

REF

and f

are consid-

ered spurious.

Note 3: For DAC SFDR measurements, the amplitude of f

REF

(10.7MHz) is compared to the amplitudes of all frequency compo-

nents of the output waveform except for f

(4.3MHz).

Note 4: For DAC measurements, THD+N is defined as the ratio of the square-root of the sum-of-the-squares of the RMS values of

all harmonic and noise components of the output waveform (except for f

and f

REF

) to the RMS amplitude of the f

REF

com-

ponent.

Note 5: Clock feedthrough is defined as the difference in amplitude between the f

REF

component and the f

CLK

component when

measured differentially from AIO+ to AIO-.

Note 6: Guaranteed by design. Not production tested.

Note 7: The DAC input interface is a master/slave register. An additional half clock cycle is required for data at the digital inputs to

propagate through to the DAC switches.

Note 8: RXEN = 1, TXEN = 0. Unless otherwise noted, for all receive ADC measurements, the analog input signal is applied differ-

entially from AIO+ to AIO-, specified using the Best-Fit Straight-Line Linearity method.

Note 9: f

= 10.7MHz, f

CLK

= 15MHz. Amplitude is 1dB below full-scale. The reference frequency (f

REF

) is defined to be 4.3MHz

CLK

- f

). All components except for f

REF

and f

are considered spurious.

Note 10: Receive ADC THD measurements include the first five harmonics.

Note 11: CAUTION: Operation of the analog inputs AIO+ and AIO- (pins 4 and 5) at more than 1.5V below VCCA could cause

latchup and possible destruction of the part. Avoid shunt capacitances to GND on these pins. If shunt capacitances are

required, then bypass these pins only to VCCA.

Note 12: All digital input signals are measured from 50% amplitude reference points. All digital output signal propagation delays are

measured to V

OH(AC)

for rising output signals and to V

OL(AC)

for falling output signals. The values for V

OH(AC)

and V

OL(AC)

as a function of the VCCD supply are shown in the following table:

VCCD (V)

OH(AC)

(V) V

OL(AC)

(V)

2.7 to 3.3 VCCD - 1.1 0.5

3.3 to 5.5 2/3 x VCCD 0.5

TIMING CHARACTERISTICS (Data Outputs: R

= 1MΩ, C

= 15pF, T

= T

MIN

to T

MAX

, unless otherwise noted.) (Note 12)

MAX1005

IF Undersampler

_______________________________________________________________________________________

-0.50

-0.30

-0.40

-0.10

-0.20

0.10

0.00

0.20

0.40

0.30

0.50

-15 -9 -6 -3-12 0 3 6 129 15

RECEIVE ADC

INTEGRAL NONLINEARITY

MAX1005-01

CODE

INL (LSB)

-0.50

-0.30

-0.40

-0.10

-0.20

0.10

0.00

0.20

0.40

0.30

0.50

-15 -9 -6 -3-12 0 3 6 129 15

RECEIVE ADC

DIFFERENTIAL NONLINEARITY

MAX1005-02

CODE

DNL (LSB)

-0.5

-0.3

-0.4

-0.1

-0.2

0.1

0.2

0.4

0.3

0.5

-64 -32 -16-48 0 16 32 48 64

TRANSMIT DAC

INTEGRAL NONLINEARITY

MAX1005-03

CODE

INL (LSB)

-0.5

-0.3

-0.4

-0.1

-0.2

0.1

0.2

0.4

0.3

0.5

-64 -32 -16-48 0 16 32 48 64

TRANSMIT DAC

DIFFERENTIAL NONLINEARITY

MAX1005-04

CODE

DNL (LSB)

-70

-40

-50

-60

-30

-20

-10

0 2.9301.465 4.395 5.860 7.325

RECEIVE ADC FFT PLOT

MAX1005-05

FREQUENCY (MHz)

AMPLITUDE (dB)

= 10.7MHz

CLK

= 15MHz

256 POINTS

-7

-6

-5

1 10 100

FULL POWER ANALOG

INPUT BANDWIDTH

MAX1005-06

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

-4

-3

-2

-1

= 90% OF FULL SCALE

__________________________________________Typical Operating Characteristics

(VCCA = VCCD = 3.0V, T

= +25°C, unless otherwise noted.)

MAX1005

_______________Detailed Description

The MAX1005 is designed to operate with the Maxim

PWT1900 (TAG-6) wireless transceiver chipset consisting

of the MAX2411 RF transceiver, the MAX2511 IF trans-

ceiver, and the MAX1007 power-control/diversity IC. The

MAX1005 integrates all the functions of an IF undersam-

pler into a single low-power integrated circuit. It is also

well suited for other time-division duplex (TDD) communi-

cations systems. This device includes a 7-bit transmit

DAC, a 5-bit receive ADC, two internal bandgap refer-

ences, clock drivers, and all necessary interface and

control logic.

Transmit DAC

The low-side alias frequency (f

CLK

- f

OUT

= 10.7MHz)

generated by the MAX1005’s 7-bit DAC is used to recre-

ate the IF sub-carrier and transmission data in TDD and

other communications systems. The DAC accepts CMOS

input data in the twos-complement format and outputs a

corresponding analog voltage differentially between

AIO+ and AIO-. The full-scale output voltage range is typ-

ically ±400mV. The DAC code table is shown in Table 1.

Table 1. Transmit DAC Code Table

Receive ADC

The 5-bit receive ADC is used to directly sample or

undersample a downconverted RF signal. The ADC

converts an analog input signal to a 5-bit digital output

code in the twos-complement format. Figure 1 shows

the ADC transfer function.

Analog input signals are applied differentially between

AIO+ and AIO-, with a full-scale range of ±200mV. An

internal amplifier buffers the input signal and drives the

comparator array, minimizing loading on the external

signal source. The input amplifier has a full-power -1dB

bandwidth of at least 15MHz, making this device ideally

suited for undersampling applications.

IF Undersampler

6 _______________________________________________________________________________________

______________________________________________________________Pin Description

Two MSBs for DAC input data. D6 is the MSB.D6, D59, 10

Data Input/Output Pins. If RXEN = 0 and TXEN = 1, then D4–D0 function as the five lower bits of DAC input

data, with D0 as the LSB. If RXEN = 1 and TXEN = 0, then D4–D0 function as the five data outputs for the

ADC, with D4 as the MSB and D0 as the LSB. In low-power shutdown mode (RXEN = TXEN), D0–D4 should

not be externally held high, to prevent excessive input leakage currents.

D4–D011–15

Clock Input. If the receive ADC is active (RXEN = 1, TXEN = 0), the analog input is sampled on the falling

edge of clock and the data outputs (D4-D0) are updated on the rising edge of CLK. If the transmit DAC is

active (TXEN = 1, RXEN = 0), input data is clocked in on the falling edge of CLK and the DAC output is

updated on the rising edge of CLK. The input clock may continue to run when the MAX1005 is shut down

(TXEN = RXEN).

CLK16

Negative Analog Input/Output Pin. If RXEN = 1 and TXEN = 0, then AIO- is the negative analog input to the

receive ADC. If RXEN = 0 and TXEN = 1, then AIO- is the negative transmit DAC output pin.

AIO-5

Transmit DAC Enable Input. A logic-high level on this input combined with a logic-low level on RXEN

enables the transmit DAC and disables the receive ADC. If RXEN = TXEN, the MAX1005 enters its low-

power shutdown mode.

TXEN6

Analog Ground. Connect to analog ground plane.AGND7

Analog Supply Voltage, +2.7V to +5.5VVCCA8

Positive Analog Input/Output Pin. If RXEN = 1 and TXEN = 0, then AIO+ is the positive analog input to the

receive ADC. If RXEN = 0 and TXEN = 1, then AIO+ is the positive transmit DAC output pin.

AIO+4

Receive ADC Enable Input. A logic-high level on this input combined with a logic-low level on TXEN enables

the receive ADC and disables the transmit DAC. If RXEN = TXEN, the MAX1005 enters its low-power shut-

down mode.

RXEN3

Digital Ground. Connect to digital ground plane.DGND2

Digital Supply Voltage, +2.7V to +5.5VVCCD

FUNCTIONNAME

DAC INPUT DATA ANALOG OUTPUT

011 1111 +FS

000 0000 0

100 0000 -FS

P1-P3 P4-P6 P7-P8

MAX1005EEE+T

Mfr. #:

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Manufacturer:

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IC UNDERSAMPLER IF 16-QSOP

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MAX1005EEE+T

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