LTC2452
10
2452fd
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applicaTions inForMaTion
2) After the 16th bit is read, the user can choose one of
two ways to begin a new conversion. First, one can
pull CS high (CS = ). Second, one can use a high-low
transition on SCK (SCK = ).
3) At any time during the Data Output state, pulling CS
high (CS = ) causes the part to leave the I/O state,
abort the output and begin a new conversion.
4) When SCK = HIGH, it is possible to monitor the conver
-
sion status
by pulling CS low
and watching for SDO to
go low. This feature is available only in the idle-high
(CPOL = 1) mode.
Serial Clock Idle-High (CPOL = 1) Examples
In Figure 6, following a conversion cycle the LTC2452
automatically enters the low power sleep mode. The user
can monitor the conversion status at convenient intervals
using CS and SDO.
Pulling CS LOW while SCK is HIGH tests whether or not
the chip is in the CONVERT state. While in the CONVERT
state, SDO is HIGH while CS is LOW. In the SLEEP state,
SDO is LOW while CS is LOW. These tests are not required
operational steps but may be useful for some applications.
When the data
is available, the user applies 16 clock cycles
to transfer the result. The CS rising edge is then used to
initiate a new conversion.
The operation example of Figure 7 is identical to that of
Figure 6, except the new conversion cycle is triggered by
the falling edge of the serial clock (SCK). A 17th clock
pulse is used to trigger a new conversion cycle.
Serial Clock Idle-Low (CPOL = 0) Examples
In Figure 8, following a conversion cycle the LTC2452
automatically enters the low-power sleep state. The user
determines data availability (and the end of conversion)
Figure 6. Idle-High (CPOL = 1) Serial Clock Operation Example.
The Rising Edge of CS Starts a New Conversion
Figure 7. Idle-High (CPOL = 1) Clock Operation Example.
A 17th Clock Pulse is Used to Trigger a New Conversion Cycle
D
15
clk
1
clk
2
clk
3
clk
4
clk
15
clk
16
D
14
D
13
D
12
D
2
D
1
D
0
SD0
SCK
CONVERT CONVERTSLEEP DATA OUTPUT
2452 F06
CS
D
15
D
14
D
13
D
12
D
2
D
1
D
0
SD0
clk
1
clk
2
clk
3
clk
4
clk
15
clk
16
clk
17
SCK
CONVERT CONVERTSLEEP DATA OUTPUT
2452 F07
CS
LTC2452
11
2452fd
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applicaTions inForMaTion
based upon external timing. The user then pulls CS low
(CS = ) and
uses 16 clock cycles to transfer the result.
Following the 16th rising edge of the clock, CS is pulled high
(CS = ), which triggers a new conversion.
The
timing
diagram in Figure 9 is identical to that of Figure 8,
except in this case a new conversion is triggered by SCK.
The 16th SCK falling edge triggers a new conversion cycle
and the CS signal is subsequently pulled high.
Examples of Aborting Cycle Using CS
For some applications, the user may wish to abort the I/O
cycle and begin a new conversion. If the LTC2452 is in
the data output state, a CS rising edge clears the remain
-
ing data bits from the output registers, aborts the output
cycle
and triggers a new conversion. Figure 10 shows
an example of aborting an I/O with idle-high (CPOL = 1)
and Figure 11 shows an example of aborting an I/O with
idle-low (CPOL = 0).
A new conversion cycle can be triggered using the CS
signal without having to generate any serial clock pulses
as shown in Figure 12. If SCK is maintained at a low logic
level, after the
end of a conversion cycle, a new conver-
sion
operation
can be triggered by pulling CS low and
then high. When CS is pulled low (CS = LOW), SDO will
output the sign (D15) of the result of the just completed
conversion. While a low logic level is maintained at SCK
Figure 9. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge Triggers a New Conversion
Figure 8. Idle-Low (CPOL = 0) Clock. CS Triggers a New Conversion
D
15
D
14
D
13
D
12
D
2
D
1
D
0
clk
1
clk
2
clk
3
clk
4
clk
14
clk
15
clk
16
SCK
SD0
CONVERT CONVERTSLEEP DATA OUTPUT
2452 F08
CS
D
15
D
14
D
13
D
12
D
2
D
1
D
0
SD0
clk
1
clk
2
clk
3
clk
4
clk
15
clk
14
clk
16
SCK
CONVERT CONVERTSLEEP DATA OUTPUT
2452 F09
CS
LTC2452
12
2452fd
For more information www.linear.com/LTC2452
applicaTions inForMaTion
Figure 11. Idle-Low (CPOL = 0) Clock and Aborted I/O Example
Figure 12. Idle-Low (CPOL = 0) Clock and Minimum Data Output Length Example
Figure 10. Idle-High (CPOL = 1) Clock and Aborted I/O Example
D
15
D
14
D
13
clk
1
clk
2
clk
4
clk
3
CONVERT CONVERTSLEEP DATA OUTPUT
2452 F10
SD0
SCK
CS
D
15
D
14
D
13
SD0
clk
1
clk
2
clk
3
SCK
CONVERT CONVERTSLEEP DATA OUTPUT
2452 F11
CS
SCK = LOW
SD0
CONVERT CONVERTSLEEP DATA OUTPUT
2452 F12
D
15
CS

LTC2452CDDB#TRMPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-bit 60Hz SPI Differential Ultra-Tiny Delta Sigma ADC
Lifecycle:
New from this manufacturer.
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