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LTC2452CTS8#TRMPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
LTC2452
13
2452fd
For more information www.linear.com/LTC2452
pin and CS is subsequently pulled high (CS = HIGH) the
remaining 15 bits of the result (D14:D0) are discarded
and a new conversion cycle starts.
Following the aborted I/O, additional clock pulses in the
CONVERT state are acceptable, but excessive signal tran
-
sitions on SCK can potentially create noise on the ADC
during
the conversion, and thus may negatively influence
the conversion accuracy.
2-Wire Operation
The 2-wire operation modes, while reducing the number
of required control signals, should be used only if the
LTC2452 low power sleep capability is not required. In
addition the option to abort serial data transfers is no
longer available. Hardwire CS to GND for 2-wire operation.
Figure 13 shows a 2-wire operation sequence which uses
an idle-high (CPOL = 1) serial clock signal. The conversion
Figure 13. 2-Wire, Idle-High (CPOL = 1) Serial Clock, Operation Example
status can be monitored at the SDO output. Following a
conversion cycle, the ADC enters SLEEP state and the
SDO output transitions from HIGH to LOW. Subsequently
16 clock pulses are applied to the SCK input in order
to serially shift the 16 bit result. Finally, the 17th clock
pulse is applied to the SCK input in order to trigger a new
conversion cycle.
Figure 14 shows a 2-wire operation sequence which uses
an idle-low (CPOL = 0) serial clock signal. The conversion
status cannot be monitored at the SDO output. Following
a conversion cycle, the LTC2452 bypasses the SLEEP
state and immediately enters the DATA OUTPUT state. At
this moment the SDO pin outputs the sign (D15) of the
conversion result. The user must use external timing in
order to determine the end of conversion and result avail
-
ability. Subsequently 16 clock pulses are applied to SCK
in order to serially shift the 16-bit result. The 16th clock
falling edge triggers a new conversion cycle.
applicaTions inForMaTion
Figure 14. 2-Wire, Idle-Low (CPOL = 0) Serial Clock Operation Example
2452 F13
D
15
D
14
D
13
D
12
D
2
D
1
D
0
SD0
clk
1
clk
2
clk
3
clk
4
clk
15
clk
16
clk
17
SCK
CONVERT CONVERT
SLEEP
DATA OUTPUT
CS = LOW
2452 F14
D
15
D
14
D
13
D
12
D
2
D
1
D
0
SD0
CS = LOW
clk
1
clk
2
clk
3
clk
14
clk
4
clk
15
clk
16
SCK
CONVERT CONVERTDATA OUTPUT
LTC2452
14
2452fd
For more information www.linear.com/LTC2452
applicaTions inForMaTion
PRESERVING THE CONVERTER ACCURACY
The LTC2452 is designed to minimize the conversion
result’s sensitivity to device decoupling, PCB layout,
anti-aliasing circuits, line and frequency perturbations.
Nevertheless, in order to preserve the high accuracy capa
-
bility of
this part, some simple precautions are desirable.
Digital Signal Levels
Due
to the nature of CMOS logic, it is advisable to keep input
digital signals near GND or V
CC
. Voltages in the range of
0.5V to V
CC
– 0.5V may result in additional current leakage
from the part. Undershoot and overshoot should also be
minimized, particularly while the chip is converting. It is
thus beneficial to keep edge rates of about 10ns and limit
overshoot and undershoot to less than 0.3V.
Noisy external circuitry can potentially impact the output
under 2-wire operation. In particular, it is possible to get
the LTC2452 into an unknown state if an SCK pulse is
missed or noise triggers an extra SCK pulse. In this situ
-
ation, it is impossible to distinguish SDO = 1 (indicating
conversion in progress) from valid “1” data bits. As such,
CPOL = 1 is recommended for the 2-wire mode. The user
should look for SDO = 0 before reading data, and look
for SDO = 1 after
reading data. If SDO does not return a
“0”
within the maximum conversion time (or return a “1”
after a full data read), generate 16 SCK pulses to force a
new conversion.
Driving V
CC
and GND
In relation to the V
CC
and GND pins, the LTC2452 com-
bines internal
high frequency decoupling with damping
elements, which reduce the ADC performance sensitivity
to PCB layout and external components. Nevertheless, the
very high accuracy of this converter is best preserved by
careful low and high frequency power supply decoupling.
A 0.1µF, high quality, ceramic capacitor in parallel with
a 10µF ceramic capacitor should be connected between
the V
CC
and GND pins, as close as possible to the pack-
age. The 0.1µF capacitor
should be placed closest to the
ADC package. It is also desirable to avoid any via in the
circuit path, starting from the converter V
CC
pin, passing
through these two decoupling capacitors, and return-
ing to
the converter GND pin. The area encompassed
by
this circuit path, as well as the path length, should
be minimized.
Furthermore, as shown in Figure 15, GND is used as the
negative reference voltage. It is thus important to keep the
GND line quiet and
connect GND through a low-impedance
trace.
Very low impedance ground and power planes, and star
connections at both V
CC
and GND pins, are preferable. The
V
CC
pin should have two distinct connections: the first to
the decoupling capacitors described above, and the second
to the ground return for the power supply voltage source.
Driving REF
A simplified equivalent circuit for REF is shown in Figure
15. Like all other A/D converters, the LTC2452 is only
as accurate as the reference it is using. Therefore, it is
important to keep the reference line quiet by careful low
and high frequency decoupling.
The LT6660 reference is an ideal match for driving the
LTC2452’s REF pin. The LTC6660 is available in a 2mm
× 2mm DFN package with 2.5V, 3V, 3.3V and 5V options.
Figure 15. LTC2452 Analog Input/Reference Equivalent Circuit
R
SW
15k
(TYP)
I
LEAK
I
LEAK
V
CC
V
CC
V
CC
V
CC
C
EQ
0.35pF
(TYP)
IN
+
IN
–
GND
REF
2452 F15
R
SW
15k
(TYP)
I
LEAK
I
LEAK
R
SW
15k
(TYP)
I
LEAK
I
LEAK
R
SW
15k
(TYP)
I
LEAK
I
LEAK
LTC2452
15
2452fd
For more information www.linear.com/LTC2452
applicaTions inForMaTion
A 0.1µF, high quality, ceramic capacitor in parallel with a
10µF ceramic capacitor should be connected between the
REF and GND pins, as close as possible to the package.
The 0.1µF capacitor should be placed closest to the ADC.
Driving V
IN
+
and V
IN
–
The input drive requirements can best be analyzed using
the equivalent circuit of Figure 16. The input signal V
SIG
is
connected to the ADC input pins (IN
+
and IN
–
) through an
equivalent source resistance R
S
. This resistor includes both
the actual generator source resistance and any additional
optional resistors connected to the input pins. Optional
input capacitors C
IN
are also connected to the ADC input
pins. This capacitor is placed in parallel with the ADC
input parasitic capacitance C
PAR
. Depending on the PCB
layout, C
PAR
has typical values between 2pF and 15pF. In
addition, the equivalent circuit of Figure 16 includes the
converter equivalent internal resistor R
SW
and sampling
capacitor C
EQ
.
There are some immediate trade-offs in R
S
and C
IN
without
needing a full circuit analysis. Increasing R
S
and C
IN
can
give the following benefits:
1) Due to the LTC2452’s input sampling algorithm, the input
current
drawn by either V
IN
+
or V
IN
–
over a conversion
cycle is typically 50nA. A high R
S
• C
IN
attenuates the
high frequency components of the input current, and
R
S
values up to 1k result in <1LSB error.
Figure 16. LTC2452 Input Drive Equivalent Circuit
2) The bandwidth from V
SIG
is reduced at the input pins
(IN
+
, IN
–
). This bandwidth reduction isolates the ADC
from high frequency signals, and as such provides
simple anti-aliasing and input noise reduction.
3) Switching transients generated by the ADC are attenu
-
ated before they go back to the signal source.
4)
A large C
IN
gives a better AC ground at the input pins,
helping reduce reflections back to the signal source.
5) Increasing R
S
protects the ADC by limiting the current
during an outside-the-rails fault condition.
There is a limit to how large R
S
• C
IN
should be for a given
application. Increasing R
S
beyond a given point increases
the voltage drop across R
S
due to the input current,
to the point that significant measurement errors exist.
Additionally, for
some applications, increasing the R
S
• C
IN
product too much may unacceptably attenuate the signal
at frequencies of interest.
For
most applications, it is desirable to implement C
IN
as
a high-quality 0.1µF ceramic capacitor and R
S
≤ 1k. This
capacitor should be located as close as possible to the
actual V
IN
package pin. Furthermore, the area encompassed
by this circuit path, as well as the path length, should be
minimized.
I
LEAK
I
LEAK
R
SW
15k
(TYP)
I
CONV
C
IN
IN
+
V
CC
SIG
+
SIG
–
R
S
C
EQ
0.35pF
(TYP)
C
PAR
+
–
2452 F16
I
LEAK
I
LEAK
R
SW
15k
(TYP)
I
CONV
C
IN
IN
–
V
CC
R
S
C
EQ
0.35pF
(TYP)
C
PAR
+
–
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LTC2452CTS8#TRMPBF

Mfr. #:
Buy LTC2452CTS8#TRMPBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-bit 60Hz SPI Differential Ultra-Tiny Delta Sigma ADC
Lifecycle:
New from this manufacturer.
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