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September 2018 DB3707 Rev 2 1/5
SPC584Cx, SPC58ECx
32-bit Power Architecture
®
microcontroller for automotive ASIL-B
applications
Data brief
Features
AEC-Q100 qualified
High performance e200z420n3
dual core:
– 32-bit Power Architecture technology
CPU
– Core frequency as high as 180 MHz
– Variable Length Encoding (VLE)
4224 KB (4096 KB code flash + 128 KB data
flash) on-chip flash memory: supports read
during program and erases operations, and
multiple blocks allowing EEPROM emulation
176 KB HSM dedicated flash memory (144 KB
code + 32 KB data)
384 KB on-chip general-purpose SRAM (in
addition to 128 KB core local data RAM: 64 KB
included in each CPU)
Multi-channel direct memory access controller
(eDMA) with 64 channels
1 interrupt controller (INTC)
Comprehensive new generation ASIL-B safety
concept:
– ASIL-B of ISO 26262
– FCCU for collection and reaction to
failure notifications
– Memory Error Management Unit
(MEMU) for collection and reporting of
error events in memories
– Cyclic redundancy check (CRC) unit
Crossbar switch architecture for concurrent
access to peripherals, Flash, or RAM from
multiple bus masters with end-to-end ECC
Body cross triggering unit (BCTU):
– Triggers ADC conversions from any
eMIOS channel
– Triggers ADC conversions from up to 2
dedicated PIT_RTIs
Enhanced modular IO subsystem (eMIOS):
up to 64 timed I/O channels with 16-bit
counter resolution
Enhanced analog-to-digital converter system
with:
– 3 independent fast 12-bit SAR analog
converters
– 1 supervisor 12-bit SAR analog
converter
– 1 10-bit SAR analog converter with
STDBY mode support:
Communication interfaces:
– 18 LINFlexD modules
– 8 deserial serial peripheral interface
(DSPI) modules
– 8 MCAN interfaces with advanced
shared memory scheme and ISO CAN-
FD support
– Dual channel FlexRay controller
– 1 Ethernet controller 10/100 Mbps,
compliant IEEE 802.3-2008
eTQFP100 (14 x 14 x 1.0 mm)
eTQFP64 (10 x 10 x 1.0 mm)
eTQFP144 (20 x 20 x 1.0 mm)
FPBGA292 (17 x 17 x 1.8 mm)
eTQFP176 (24 x 24 x 1.4 mm)
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