LT3684
7
3684fa
For more information www.linear.com/LT3684
BD (Pin 1): This pin connects to the anode of the boost
Schottky diode.
BOOST (Pin 2): This pin is used to provide a drive
voltage, higher than the input voltage, to the internal bipolar
NPN power switch.
SW (Pin 3): The SW pin is the output of the internal power
switch. Connect this pin to the inductor, catch diode and
boost capacitor.
V
IN
(Pin 4): The V
IN
pin supplies current to the LT3684’s
internal regulator and to the internal power switch. This
pin must be locally bypassed.
RUN/SS (Pin 5): The RUN/SS pin is used to put the
LT3684 in shutdown mode. Tie to ground to shut down
the LT3684. Tie to 2.3V or more for normal operation. If
the shutdown feature is not used, tie this pin to the V
IN
pin. RUN/SS also provides a soft-start function; see the
Applications Information section.
PG (Pin 6): The PG pin is the open collector output of an
internal comparator. PG remains low until the FB pin is
within 10% of the final regulation voltage. PG output is
valid when V
IN
is above 3.5V and RUN/SS is high.
BIAS (Pin 7): The BIAS pin supplies the current to the
LT3684’s internal regulator. Tie this pin to the lowest
available voltage source above 3V (typically V
OUT
). This
architecture increases efficiency especially when the input
voltage is much higher than the output.
FB (Pin 8): The LT3684 regulates the FB pin to 1.265V.
Connect the feedback resistor divider tap to this pin.
V
C
(Pin 9): The V
C
pin is the output of the internal error
amplifier. The voltage on this pin controls the peak switch
current. Tie an RC network from this pin to ground to
compensate the control loop.
RT
(Pin 10): Oscillator Resistor Input. Connecting a resis-
tor to ground from this pin sets the switching frequency.
Exposed Pad (Pin 11): Ground. The Exposed Pad must
be soldered to PCB.
PIN FUNCTIONS
LT3684
8
3684fa
For more information www.linear.com/LT3684
The LT3684 is a constant frequency, current mode step-
down regulator. An oscillator, with frequency set by RT,
enables an RS flip-flop, turning on the internal power
switch. An amplifier and comparator monitor the current
flowing between the V
IN
and SW pins, turning the switch
off when this current reaches a level determined by the
voltage at V
C
. An error amplifier measures the output
voltage through an external resistor divider tied to the FB
pin and servos the V
C
pin. If the error amplifiers output
increases, more current is delivered to the output; if it
decreases, less current is delivered. An active clamp on the
V
C
pin provides current limit. The V
C
pin is also clamped to
the voltage on the RUN/SS pin; soft-start is implemented
by generating a voltage ramp at the RUN/SS pin using an
external resistor and capacitor.
An internal regulator provides power to the control cir-
cuitry. The bias regulator normally draws power from the
V
IN
pin, but if the BIAS pin is connected to an external
voltage higher than 3V bias power will be drawn from the
external source (typically the regulated output voltage).
This improves efficiency. The RUN/SS pin is used to place
the LT3684 in shutdown, disconnecting the output and
reducing the input current to less than 1µA.
The switch driver operates from either the input or from
the BOOST pin. An external capacitor and diode are used
to generate a voltage at the BOOST pin that is higher than
the input supply. This allows the driver to fully saturate
the internal bipolar NPN power switch for efficient
operation.
The oscillator reduces the LT3684’s operating frequency
when the voltage at the FB pin is low. This frequency
foldback helps to control the output current during startup
and overload.
The LT3684 contains a power good comparator which trips
when the FB pin is at 90% of its regulated value. The PG
output is an open-collector transistor that is off when the
output is in regulation, allowing an external resistor to pull
the PG pin high. Power good is valid when the LT3684 is
enabled and V
IN
is above 3.6V.
OPERATION
BLOCK DIAGRAM
+
+
+
OSCILLATOR
300kHz–2.8MHz
V
C
CLAMP
SOFT-START
SLOPE COMP
INTERNAL 1.265V REF
R
V
IN
V
IN
BIAS
RUN/SS
BOOST
SW
SWITCH
LATCH
V
C
V
OUT
C2
C3
C
F
L1
D1
C
C
R
C
BD
RT
R2
GND
ERROR AMP
R1
FB
R
T
C1
PG
1.12V
S
Q
3684 BD
4
7
5
10
6
1
2
3
9
11 8
LT3684
9
3684fa
For more information www.linear.com/LT3684
FB Resistor Network
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the 1% resis-
tors according to:
R1=R2
OUT
1.265
1
Reference designators refer to the Block Diagram.
Setting the Switching Frequency
The LT3684 uses a constant frequency PWM architecture
that can be programmed to switch from 300kHz to 2.8MHz
by using a resistor tied from the RT pin to ground. A table
showing the necessary R
T
value for a desired switching
frequency is in Figure 1.
SWITCHING FREQUENCY (MHz) R
T
VALUE (k)
0.2
0.3
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
267
187
133
84.5
60.4
45.3
36.5
29.4
23.7
20.5
16.9
14.3
12.1
10.2
8.66
Operating Frequency Tradeoffs
Selection of the operating frequency is a tradeoff between
efficiency, component size, minimum dropout voltage, and
maximum input voltage. The advantage of high frequency
operation is that smaller inductor and capacitor values may
be used. The disadvantages are lower efficiency, lower
maximum input voltage, and higher dropout voltage. The
highest acceptable switching frequency (f
SW(MAX)
) for a
given application can be calculated as follows:
f
SW(MAX)
=
V
D
+ V
OUT
t
ON(MIN)
V
D
+ V
IN
V
SW
( )
where V
IN
is the typical input voltage, V
OUT
is the output
voltage V
D
, is the catch diode drop (~0.5V), V
SW
is the
internal switch drop (~0.5V at max load). This equation
shows that slower switching frequency is necessary to
safely accommodate high V
IN
/V
OUT
ratio. Also, as shown
in the next section, lower frequency allows a lower dropout
voltage. The reason input voltage range depends on the
switching frequency is because the LT3684 switch has
finite minimum on and off times. The switch can turn on
for a minimum of ~150ns and turn off for a minimum of
~150ns. This means that the minimum and maximum
duty cycles are:
DC
MIN
= f
SW
t
ON(MIN)
DC
MAX
= 1 f
SW
t
OFF(MIN)
where f
SW
is the switching frequency, the t
ON(MIN)
is the
minimum switch on time (~150ns), and the t
OFF(MIN)
is
the minimum switch off time (~150ns). These equations
show that duty cycle range increases when switching
frequency is decreased.
A good choice of switching frequency should allow ad-
equate input voltage range (see next section) and keep
the inductor and capacitor values small.
Input Voltage Range
The maximum input voltage for LT3684 applications
depends on switching frequency, the Absolute Maximum
Ratings on V
IN
and BOOST pins, and on operating mode.
If the output is in start-up or short-circuit operating modes,
then V
IN
must be below 34V and below the result of the
following equation:
V
IN(MAX)
=
V
OUT
+ V
D
1 f
SW
t
ON(MIN)
V
D
+ V
SW
where V
IN(MAX)
is the maximum operating input voltage,
V
OUT
is the output voltage, V
D
is the catch diode drop
(~0.5V), V
SW
is the internal switch drop (~0.5V at max
load), f
SW
is the switching frequency (set by R
T
), and
t
ON(MIN)
is the minimum switch on time (~150ns). Note that
a higher switching frequency will depress the maximum
operating input voltage. Conversely, a lower switching
Figure 1. Switching Frequency vs R
T
Value
APPLICATIONS INFORMATION

LT3684EDD#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 36V/2A Buck (non BurstMode LT3481)
Lifecycle:
New from this manufacturer.
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