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NCP51145MNTAG

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2015
April, 2017 − Rev. 3
1 Publication Order Number:
NCP51145/D
NCP51145
DDR 1.8 Amp Source / Sink
V
TT
Termination Regulator
The NCP51145 is a linear regulator designed to supply a regulated
V
TT
termination voltage for DDR−II, DDR−III, LPDDR−III and
DDR−IV memory applications. The regulator is capable of actively
sourcing and sinking
±1.8 A peak currents while regulating an output
voltage to within
±20 mV. The output termination voltage is regulated
to track V
DDQ
/ 2 by two external voltage divider resistors connected
to the PV
CC
, GND, and V
REF
pins.
The NCP51145 incorporates a high−speed differential amplifier to
provide ultra−fast response to line and load transients. Other features
include source/sink current limiting, soft−start and on−chip thermal
shutdown protection.
Features
• For DDR V
TT
Applications, Source/Sink Currents:
• Supports DDR−II to ±1.8 A, DDR−III to ±1.5 A
• Supports LPDDR−III and DDR−IV to ±1.2 A
• Stable Using Ceramic−Only (Very Low ESR) Capacitors
• Integrated Power MOSFETs
• High Accuracy V
TT
Output at Full−Load
• Fast Transient Response
• Built−in Soft−Start
• Shutdown for Standby or Suspend Mode
• Integrated Thermal and Current−Limit Protection
• V
TT
Remote Sense Available in the DFN8 2x2mm Package
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• DDR−II / DR−III / DDR−IV SDRAM Termination Voltage
• Motherboard, Notebook, and VGA Card Memory Termination
• Set Top Box, Digital TV, Printers
• Low Power DDR−3LP
MARKING
DIAGRAMS
www.
onsemi.com
SOIC−8 EP
D SUFFIX
CASE 751BU
Device Package Shipping
†
ORDERING INFORMATION
SOIC−8
(Pb−Free)
2500 / Tape &
Reel
NCP51145PDR2G
NC
V
TT
18
NC
VREF
V
CC
GND
NCPVCC
PIN CONNECTIONS
1
8
1
8
51145
AYWWG
G
51145 = Specific Device Code
XX = Specific Device Code
M = Date Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
SOIC−8 EP
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
DFN8
MN SUFFIX
CASE 506AA
1
XXMG
G
1
(Note: Microdot may be in either location)
DFN−8
(Pb−Free)
3000 / Tape &
Reel
NCP51145MNTAG
DFN8 2x2, 0.5P
VREF
GND
18
NC
NC
V
TTS
V
TT
PVCC
(Top Views)
V
CC
NCP51145
www.onsemi.com
2
C1 = 1 to 100 nF Ceramic C4 = 10 mF Ceramic
C2 = 10 mF Ceramic R3 = Optional V
TT
Discharge Resistor
C3 = 1 mF N−Ch MOSFET = Optional Enable / Disable
Figure 1. Application Diagram
NCP51145
SO8−EP Package
PV
CC
GND
V
REF
V
CC
V
TT
C2
1
2
3
6
4
C4
C3
5 V
R3
C1
R1
100k
R2
100k
Enable
PV
CC
= 1.0 to 5.5 V*
V
TT
= 0.6 to 2.5 V*
R4
2.2
*For DDR2: PV
CC
= 1.8 V, V
TT
= 0.9 V
DDR3: PV
CC
= 1.5 V, V
TT
= 0.75 V
DDR4: PV
CC
= 1.2 V, V
TT
= 0.60 V
EP
PIN FUNCTION DESCRIPTION
Pin No.
SO8−EP
Pin No.
DFN8
Pin Name Description
1 1 PV
CC
Input voltage which supplies current to the output pin. C
IN
^ ½ S C
OUT
2 4 GND Common Ground
3 5 V
REF
Buffered reference voltage input equal to ½ of V
DDQ
and active low shutdown pin. An
external resistor divider dividing down the PV
CC
voltage creates the regulated output
voltage. Pulling the pin to ground (0.15 V maximum) turns the device off.
4 2 V
TT
Regulator output voltage capable of sourcing and sinking current while regulating the
output rail. C
OUT
= 10 mF Ceramic, or greater
5, 7, 8 3, 7 NC True No Connect
6 8 V
CC
The V
CC
pin is a 5 V input pin that provides internal bias to the controller. PV
CC
should
always be kept lower or equal to V
CC
.
− 6 V
TTS
V
TT
Sense
EP EP EPAD Pad for thermal connection. The exposed pad must be connected to the ground plane
using multiple vias for maximum power dissipation performance.
NCP51145
www.onsemi.com
3
ABSOLUTE MAXIMUM RATINGS
Rating Symbol Value Unit
Input Supply Voltage Range (V
cc
w PV
CC
) (Note 1) PV
CC
,
V
CC
−0.3 to 6 V
Output Voltage Range V
TT
−0.3 to 6 V
Reference Input Range V
REF
−0.3 to 6 V
Maximum Junction Temperature T
J(max)
150 °C
Storage Temperature Range TSTG −65 to 150 °C
ESD Capability, Human Body Model (Note 2) ESDHBM 2 kV
ESD Capability, Machine Model (Note 2) ESDMM 200 V
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 3)
T
SLD
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
THERMAL CHARACTERISTICS
Rating Symbol Value Unit
Thermal Characteristics, SO8−EP (Note 4)
Thermal Resistance, Junction−to−Air (Note 5)
Thermal Reference, Junction−to−Lead2 (Note 5)
R
q
JA
R
Y
JL
82
TBD
°C/W
4. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.
5. Values based on copper area of 645 mm
2
(or 1 in
2
) of 1 oz copper thickness and FR4 PCB substrate.
OPERATING RANGES (Note 6)
Rating
Symbol Min Max Unit
Input Voltage PV
CC
1.0 5.5 V
Bias Supply Voltage V
CC
4.75 5.25 V
Ambient Temperature T
A
−40 85 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
P1-P3P4-P6

NCP51145MNTAG

Mfr. #:
Buy NCP51145MNTAG
Manufacturer:
ON Semiconductor
Description:
Linear Voltage Regulators 1.8 AMP SOURCE SINK VTT T
Lifecycle:
New from this manufacturer.
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