STK581U3C2D-E
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8
Logic Timing Chart
Fig. 7
Notes
*1 : Diagram shows the prevention of shoot-through via control logic. More dead time to account for switching delay needs to be
added externally.
*2 : When V
DD
decreases all gate output signals will go low and cut off all of 6 IGBT outputs. When V
DD
rises the operation will
resume immediately.
*3 : When the upper side gate voltage at VB1, VB2 and VB3 drops only, the corresponding upper side output is turned off. The
outputs return to normal operation immediately after the upper side gate voltage rises.
*4 : In case of over current detection, all IGBT’s are turned off and the FAULT output is asserted. Normal operation resumes in 18 to
80 ms after the over current condition is removed.
ON
OFF
HIN1,2,3
LIN1,2,3
-terminal
(BUS line)
Current
Upper
U, V, W
Lower
U ,V, W
VB1,2,3
*1
*1
OFF
ON
*2
*3
VBS undervoltage protection reset signal
VDD undervoltage protection reset voltage
-------------------------------------------------------ISD operation current level-------------------------------------------------------
utomatically reset after protection
(18ms to 80ms)
*4
VDD
VBS undervoltage protection reset voltage
FAULT terminal
oltage
(at pulled-up)
