13
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance
for the high frequency decoupling and bulk capacitors to
supply the RMS current. Small ceramic capacitors should be
placed very close to the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances.
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-
GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
MOSFET Selection/Considerations
The HIP6018B requires 3 N-Channel power MOSFETs. Two
MOSFETs are used in the synchronous-rectified buck
topology of the PWM converter. The linear controller drives a
MOSFET as a pass transistor. These should be selected
based upon r
DS(ON)
, gate supply requirements, and thermal
management requirements.
PWM1 MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the dominant
design factors. The power dissipation includes two loss
components; conduction loss and switching loss. These losses
are distributed between the upper and lower MOSFETs
according to duty factor (see the equations below). The
conduction loss is the only component of power dissipation for
the lower MOSFET. Only the upper MOSFET has switching
losses, since the lower device turns on into near zero voltage.
The equations below assume linear voltage-current transitions
and do not model power loss due to the reverse-recovery of the
lower MOSFET’s body diode. The gate-charge losses are
proportional to the switching frequency (F
S
) and are dissipated
by the HIP6018B, thus not contributing to the MOSFETs’
temperature rise. However, large gate charge increases the
switching interval, t
SW
which increases the upper MOSFET
switching losses. Ensure that both MOSFETs are within their
maximum junction temperature at high ambient temperature by
calculating the temperature rise according to package thermal
resistance specifications. A separate heatsink may be
necessary depending upon MOSFET power, package type,
ambient temperature and air flow.
The r
DS(ON)
is different for the two previous equations even if the
type device is used for both. This is because the gate drive
applied to the upper MOSFET is different than the lower
MOSFET. Figure 14 shows the gate drive where the upper gate-
to-source voltage is approximately V
CC
less the input supply. For
+5V main power and +12VDC for the bias, the gate-to-source
voltage of Q1 is 7V. The lower gate drive voltage is +12VDC. A
logic-level MOSFET is a good choice for Q1 and a logic-level
MOSFET can be used for Q2 if its absolute gate-to-source
voltage rating exceeds the maximum voltage applied to V
CC
.
Rectifier CR1 is a clamp that catches the negative inductor
voltage swing during the dead time between the turn off of the
lower MOSFET and the turn on of the upper MOSFET. The
diode must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to omit
the diode and let the body diode of the lower MOSFET clamp
the negative inductor swing, but efficiency might drop one or
two percent as a result. The diode's rated reverse breakdown
voltage must be greater than twice the maximum input voltage.
Linear Controller MOSFET Selection
The main criteria for the selection of a transistor for the linear
regulator is package selection for efficient removal of heat.
The power dissipated in a linear regulator is:
Select a package and heatsink that maintains the junction
temperature below the maximum rating while operating at
the highest expected ambient temperature.
Additionally, if selecting a bipolar NPN transistor, insure the gain
(h
fe
) at the minimum operating temperature and given collector-
to-emitter voltage is sufficiently high as to deliver the worst-case
steady state current required by the GTL output, when the
transistor is driven with the minimum guaranteed DRIVE3
output current. For example, operating at “T” junction
temperature, 3.3V input, and 1.5V output (V
CE
= 1.8V) the
NPN’s gain should satisfy the following equation:
P
UPPER
I
O
2
r
DS ON
V
OUT
V
IN
------------------------------------------------------------
I
O
V
IN
t
SW
F
S
2
----------------------------------------------------+=
P
LOWER
I
O
2
r
DS ON
V
IN
V
OUT
–
V
IN
---------------------------------------------------------------------------------=
+12V
PGND
HIP6018B
GND
LGATE
UGATE
PHASE
V
CC
+5V OR LESS
NOTE:
NOTE:
V
GS
V
CC
Q1
Q2
+
-
FIGURE 14. OUTPUT GATE DRIVERS
V
GS
V
CC
-5V
CR1
P
LINEAR
I
O
V
IN
V
OUT
–=
h
fe
I
GTL
steady state–
I
DRIVE3
min
-----------------------------------------------------------
HIP6018B
